AB + CD = ?? A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Inputs C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 Outputs y 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 Z 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0
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- Design a combinatorial circuit that will be able to detect prime numbers given as input in binary. The input to the system will be any 4 bit binary number. The output of the circuit should be a single bit that will be 1 (high) if the input is a prime number and 0 (low) if the input is not a prime number. For example, if the input to the circuit is 0101 the output should be 1. Again if the input is 1010, the output should be 0.Excess-3 code is significant for arithmetic operations as it overcomes shortcoming encountered while using 8421 BCD code to add two decimal digits whose sum exceeds 9. Excess-3 arithmetic uses different algorithm than normal non-biased BCD or binary positional number system. An electronics company has hired your services to design a code converter that converts Binary Coded Decimal (BCD) code for it. Design the converter.DFF circuit that adds the one-bit numbers a and b in series. Design according to the Mealy model a)state diagram b)state table c)simplification with Karnaugh maps
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- Finite state machine (FSM) counter design: Design a finite state machine that detects the following sequence of serial inputs on input A: 0111. The output Y should assert every time that sequence of bits is encountered in the input stream. You may assume that input A becomes a new value (i.e., the next bit) shortly after each clock edge. Show all the steps of FSM design from the black box and state transition diagram all the way to the circuit (and all the steps in between).Hint: For example, the following series of values on A could occur. After each sequence of the desired pattern (0111) is detected (highlighted in orange or green -- see attached), output Y should assert. Start with SR state to S0111 state.Finite state machine (FSM) counter design: Design a finite state machine that detects the following sequence of serial inputs on input A: 0111. The output Y should assert every time that sequence of bits is encountered in the input stream. You may assume that input A becomes a new value (i.e., the next bit) shortly after each clock edge. Show all the steps of FSM design from the black box and state transition diagram all the way to the circuit (and all the steps in between). Hint: For example, the following series of values on A could occur. After each sequence of the desired pattern (0111) is detected (highlighted in orange or green -- see attached), output Y should assert. A: 0101001110010111011100101001000100111111010111011010111011111110111011101Design a combinational circuit that accepts a four-bit number (A,B,C,D) and generates 3 output (X,Y,Z) which is equal to the sum of the binary numbers formed by the input (AB) and (CD). HENT:(AB + CD ??)