A Finite State Machine outputs a logic 1 every time two or more consecutive logic 1's are input. It will similarly output a logic 1 every time two or more consecutive logic 0's are input.  I need to find a Moore FSM state diagram for this specification. I also need a Mealy FSM state diagram.  I keep messing this up as I am still triying to learn this concept. Could you help figure this out?

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