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A & B answers are given below please Answer C part  Algorithm – We are taking first element of array in A Comparing A with other elements of array, if A is smaller then store that element in A otherwise compare with next element The value of A is the answer A Solution

A & B answers are given below please Answer C part  Algorithm – We are taking first element of array in A Comparing A with other elements of array, if A is smaller then store that element in A otherwise compare with next element The value of A is the answer A Solution

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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A & B answers are given below please Answer C part 

Algorithm –

  1. We are taking first element of array in A
  2. Comparing A with other elements of array, if A is smaller then store that element in A otherwise compare with next element
  3. The value of A is the answer

A Solution

2000

LXI H 2050

H←20, L←50

2003

MOV C, M

C←M

2004

DCR C

C←C-01

2005

INX H

HL←HL+0001

2006

MOV A, M

A←M

2007

INX H

HL←HL+0001

2008

CMP M

A-M

2009

JNC 200D

If Carry Flag=0, goto 200D

200C

MOV A, M

A←M

200D

DCR C

C←C-1

200E

JNZ 2007

If Zero Flag=0, goto 2007

2011

STA 3050

A→3050

2014

HLT

  

 

Part (b)

Pipeline-

The pipeline is the implementation technique where multiple instructions are executed simultaneously. It is highly efficient and improves overall performance.
In a pipelined processor, the pipeline has two ends the input end and the output end. Between both ends, there are many stages, where one stage is connected to another stage. The common clock controls all the stages in the pipeline along with the interface register.

The five stages of the pipeline are

  1. IF(instruction fetch)
  2. ID(instruction decode)
  3. RR(register read)
  4. EX(execute instruction)
  5. WB(Write back result into the register)

 

 

The processor has 5 stages of the pipeline.

Stage 1 

IF(instruction fetch)

It fetches the instruction to be executed from the address available in the memory whose value is present in the program counter. The program counter(PC) keeps track of instructions that are being fetched. At every clock cycle from the instruction memory, the instructions are fetched.

Stage 2

ID(instruction decode)
It decoded the instruction and execute it. The 16-bit instructions will be divided into several parts.

Stage 3

RR(register read)

In this stage, it calculates the address of read register and that address sends to the register. Data from the register is read and send to the next unit.

Stage 4

EX(execute instruction)

It executes the instructions.ALU operations are performed in this stage. 

Stage 5

WB(Write back result into the register)

After executing the instruction the result is written into the register. It is used to write any data from the instruction or storing the result of the ALU to the register.

A         Instruction Set Architecture

A.1        Instruction set

We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a.

 

 

LOAD a, b                    a <- b

STOR a, b                    a <- b

ADD a, b, c               a <- b + c

 

ASH a, b, c               a <- (b >>[s] c)

LSH a, b, c               a <- (b >>[u] c) BR a               PC <- a

 

SUB

a,

b,

c

a

<-

b

- c

BEQ

a,

b,

c

PC

<-

a

if

b =

c

MUL

a,

b,

c

a

<-

b

* c

BNE

a,

b,

c

PC

<-

a

if

not

b = c

DIV

a,

b,

c

a

<-

b

/ c

BLT

a,

b,

c

PC

<-

a

if

b <

c

AND

a,

b,

c

a

<-

b

& c

BGT

a,

b,

c

PC

<-

a

if

b >

c

 

OR a, b, c                 a <- b | c

NOT a, b                      a <- !b

 

BLE a, b, c               PC <- a if b <= c BGE a, b, c            PC <- a if b >= c

 

 

Note:  Here b >>[s]  c denotes the arithmetical shift of b to the right by c positions, and

b >>[u]  c denotes the logical shift of b to the right by c positions.

 

A.2       The pipeline

We will use a five-stage pipeline:

  • IF (instruction fetch),
  • ID (instruction decode),
  • RR (register read),
  • EX (execute instruction),
  • WB (write back result into register).
  • Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not

 

 

 

 

A.3       Execution rules

The rules for the execution of instructions are as follows:

  1. All instructions go through the IF and ID stages
  2. For data-movement instructions the data transfer between the CPU and main mem- ory happens in the execute stage. (This means that if a data transfer operation is executing, no data can be transferred across the main-memory )
  3. Immediate addressing for input arguments does not require RR or EX (e.g., LOAD r1, #X).
  4. Arithmetic and logic instructions need RR, EX and
  5. Branching operations require RR, EX and WB, unless all operands are immediate, in which case only EX and WB are
  6. For the instruction LOAD a, b the argument b must be an immediate address or memory location and a must be a
  7. For the instruction STOR a, b the argument b must be an immediate address or register and a must be a memory
  8. For each of the remaining instructions the arguments a, b and c must all be registers or immediate
  9. You may assume for the sake of the questions that the ISA supports floating point arithmetic with no loss of precision
Questions 1. The function L is defined as L(1) = 2,L(2) = 1,1(3) = 3,L(4) = 4 and for n 2 4, Lin) + L(n – 1) + L(n – 2) Ytn + 11 Lin - 3) i.e., the (n + 1}-th value is given by the sum of the n-th, n-1-th and n– 2-th values divided by the n-3-th value. (a) Write an assembly program for computing the k-th value Lik), where k is an integ er bigger than 4 and read from a memory location M, and storing L(k) at memory location M. Use the instruction set in the Instruction Set Architecture described in Appendix A. (b) Consider a pipelined processor, where the pipeline stages are those described in the appendix. Describe what ha ppens in the pipeline stages for the various types (data movement, data processing, control) of instructions. (c) Show the execution of your program on the above pipelined processor for k = 6 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with unlimited capacity (and so you can store any number of instruction in the IW). Explain where and why delay slots appear. execution to speed up the completion of the program. Assume that there is only one bus, and that the fetching of instructions uses this bus. So the fetching of an instruction can conflict with a stage where an instruc tion Assum e that the processor do out-of-order can accesses memory.
Transcribed Image Text:Questions 1. The function L is defined as L(1) = 2,L(2) = 1,1(3) = 3,L(4) = 4 and for n 2 4, Lin) + L(n – 1) + L(n – 2) Ytn + 11 Lin - 3) i.e., the (n + 1}-th value is given by the sum of the n-th, n-1-th and n– 2-th values divided by the n-3-th value. (a) Write an assembly program for computing the k-th value Lik), where k is an integ er bigger than 4 and read from a memory location M, and storing L(k) at memory location M. Use the instruction set in the Instruction Set Architecture described in Appendix A. (b) Consider a pipelined processor, where the pipeline stages are those described in the appendix. Describe what ha ppens in the pipeline stages for the various types (data movement, data processing, control) of instructions. (c) Show the execution of your program on the above pipelined processor for k = 6 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with unlimited capacity (and so you can store any number of instruction in the IW). Explain where and why delay slots appear. execution to speed up the completion of the program. Assume that there is only one bus, and that the fetching of instructions uses this bus. So the fetching of an instruction can conflict with a stage where an instruc tion Assum e that the processor do out-of-order can accesses memory.
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