a) A logic circuit shown in Figure Q.3 has a 4-bit input A and B, three 4-bit wide 2:1 muxes, a 4-bit adder, a 4-bit output F, and a carry flag C. For the given Table Q.3, fill in the value of output F and carry flag C for the given value of A, B, S0, S1 and S2. 52 1001 FlagC 0011 Figure Q.3 Table Q.3 Elag C

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(a) A logic circuit shown in Figure Q.3 has a 4-bit input A and B, three 4-bit wide 2:1 muxes, a
4-bit adder, a 4-bit output F, and a carry flag C. For the given Table Q.3, fill in the value of
output F and carry flag C for the given value of A, B, S0, S1 and S2.
51
52
1001
Flag C
0011
Figure Q.3
Table Q.3
A
So
S1
S2
F
Flag C
0001
1000
0010
1001
1
1
0011
1101
0100
1101
1110
0111
1
Transcribed Image Text:(a) A logic circuit shown in Figure Q.3 has a 4-bit input A and B, three 4-bit wide 2:1 muxes, a 4-bit adder, a 4-bit output F, and a carry flag C. For the given Table Q.3, fill in the value of output F and carry flag C for the given value of A, B, S0, S1 and S2. 51 52 1001 Flag C 0011 Figure Q.3 Table Q.3 A So S1 S2 F Flag C 0001 1000 0010 1001 1 1 0011 1101 0100 1101 1110 0111 1
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