(a) A 64K X 16 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. (Cip RAM 64K X 16 menggunakan penyahkodan secara kebetulan dengan membahagikan penyahkod dalaman kepada pilih baris dan pilih tajur.] i) Determine the size of each decoder, and how many AND gates are required for decoding and address? Assuming that the RAM cell array is square. (Tentukan saiz setiap penyahkod, dan berapa banyak get AND yang diperlukan untuk penyahkodan dan alamat? Dengan mengandaikan bahawa tatasusunan sel RAM adalah segi empat sama.]

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Question 2
[Soalan 2]
(С6, СОЗ, РОЗ)
(a) A 64K X 16 RAM chip uses coincident decoding by splitting the internal decoder into row select
and column select.
(Cip RAM 64K X 16 menggunakan penyahkodan secara kebetulan dengan membahagikan penyahkod dalaman
kepada pilih baris dđan pilih lajur.]
i)
Determine the size of each decoder, and how many AND gates are required for decoding
and address? Assuming that the RAM cell array is square.
(Tentukan saiz setiap penyahkod, dan berapa banyak get AND yang diperlukan untuk penyahkodan
dan alamat? Dengan mengandaikan bahawa tatasusunan sel RAM adalah segi empat sama.]
ii)
Demonstrate the row and column selection lines that are enabled when the input address
is the binary equivalent of (32000)10.
[Tentukan baris pemilihan baris dan lajur yang dibolehkan apabila alamat input adalah bersamaan binari
(32000)o.
(b) Design the complete block diagram for 128K x 16 RAM by using a decoder and the RAM chip
in Figure 1.
(Rekabentuk gambarajah blok lengkap bagi RAM 128K x 16 dengan menggunakan penyahkod dan cip RAM dalam
Rajah 1)
32К x 8
8
DATA
15
ADRS
Input data-
-Output data
Address-
Chip select-
CS
Read/Write
RAW
Figure 1
(Rajah 1]
Transcribed Image Text:Question 2 [Soalan 2] (С6, СОЗ, РОЗ) (a) A 64K X 16 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. (Cip RAM 64K X 16 menggunakan penyahkodan secara kebetulan dengan membahagikan penyahkod dalaman kepada pilih baris dđan pilih lajur.] i) Determine the size of each decoder, and how many AND gates are required for decoding and address? Assuming that the RAM cell array is square. (Tentukan saiz setiap penyahkod, dan berapa banyak get AND yang diperlukan untuk penyahkodan dan alamat? Dengan mengandaikan bahawa tatasusunan sel RAM adalah segi empat sama.] ii) Demonstrate the row and column selection lines that are enabled when the input address is the binary equivalent of (32000)10. [Tentukan baris pemilihan baris dan lajur yang dibolehkan apabila alamat input adalah bersamaan binari (32000)o. (b) Design the complete block diagram for 128K x 16 RAM by using a decoder and the RAM chip in Figure 1. (Rekabentuk gambarajah blok lengkap bagi RAM 128K x 16 dengan menggunakan penyahkod dan cip RAM dalam Rajah 1) 32К x 8 8 DATA 15 ADRS Input data- -Output data Address- Chip select- CS Read/Write RAW Figure 1 (Rajah 1]
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