8.3 An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2'scomplement data. Do the following:LD addressIIAcc - Memory [address], read from LM2IIAcc - data (a 2's complement number, sign extended)IIAcc - Acc + data (data is a 2's complement number, sign extended)IIAcc - Acc - data (data is a 2's complement number, sign extended)IIAc-LD dataADD dataSUB dataADD (address)STM (address)SUB (address)JMP addressAcc + Memory[address]IIM[address] - AccIIAcc - Acc - Memory[address]//PP - addressJZ addressa) Draw a data path for the CPU assuming the DM has separate input and output bus as in the datapath shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (40 pts)

8.3 An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2's complement data. Do the following: LD address IIAcc - Memory [address], read from LM2 IIAcc - data (a 2's complement number, sign extended) IIAcc - Acc + data (data is a 2's complement number, sign extended) IIACC - Acc - data (data is a 2's complement number, sign extended) IIAcc - Acc + Memory[address] I/M[address] - Acc IIACC - Acc - Memory[address] I/PP - address LD data ADD data SUB data ADD (address) STM (address) SUB (address) JMP address JZ address a) Draw a data path for the CPU assuming the DM has separate input and output bus as in the data path shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (40 pts)

8.3 An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2's complement data. Do the following: LD address IIAcc - Memory [address], read from LM2 IIAcc - data (a 2's complement number, sign extended) IIAcc - Acc + data (data is a 2's complement number, sign extended) IIACC - Acc - data (data is a 2's complement number, sign extended) IIAcc - Acc + Memory[address] I/M[address] - Acc IIACC - Acc - Memory[address] I/PP - address LD data ADD data SUB data ADD (address) STM (address) SUB (address) JMP address JZ address a) Draw a data path for the CPU assuming the DM has separate input and output bus as in the data path shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (40 pts)

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

What is the addressing mode of the following instruction? ADD [BX],DI Select one: a. b. d. e. Register addressing mode Base plus index addressing mode Relative base plus index addressing mode Relative register addressing mode Indirect addressing mode
1. Write an instruction sequence to save the current content of the flag in memory location MEM1 and then reload the flags with the contents of memory location MEM2. LAHF MOV MEM1, AH MOV AH, MEM2 SAHF HLT 2. Verify the operation of the following instructions that affect carry flag, start with CF = 0. CLC STC СМС 3. Write an instruction sequence to configure the 8086 as follows: Interrupts not accepted; Save the original contents of flag SF,ZF,AF,PF and CF at the address [0700H], then Clear the carry.
Carider the data path below for a single cyde 32-bits MIPS processor Amume that we are ecuing the folowing instruction ADD $2, S3, Suo What is the value of the element pointed by awrow number 1 by in hexadecimal? Note that the PC and the content of registers SID and S1 are found in bottom left of the fgre below Address Content OK000016EC ON0000ABOD Data Memory OX000016FO ON0OA01245 OX000016F4 Ox00001A42 MentaFlagy Conte Ox000171C ON00OB124F Ox0001720 Ox00021345 Fead Ox0001724 OX000067AB ALU Ox0001734 OX0000AB35 meory Ox0001738 ONO000FA72 Ox000174C ON0000ABOC $s0 = OX0000AFO0 $s2 = OX00000OBA $s3 = Ox00000001 Register File and PC PC = OX000FAC04 (Before executing ADD) li li
microprocessor 8086
:- We will be implementing a new instruction within the MIPS architecture. New instruction will decrement a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation: Reg[Rt]= Mem[4*Rs+Offset] - 1 Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)
1. 6502 assembly language references data in memory locations using an operand value containing the address (without the # character that indicates an immediate value). For example, the LDA $00 instruction loads the byte at memory address $00 into A. STA $01 stores the byte in A into address $01. Addresses can be any value in the range 0 to SFFFF, assuming memory exists at the address and the address is not already in use for some other purpose. Using your preferred 6502 emulator, write 6502 assembly code to store a 16-bit value into addresses $00-$01, store a second value into addresses $02-$03, then add the two values and store the result in $04-$05. Be sure to propagate any carry between the two bytes. Ignore any carry from the 16-bit result. Test with $0000+$0001, $00FF+$0001, and $1234+$5678.
Microprocessors 8086
subject is Microprocessor - Arithmetic Instructions
witch of the following is the mode of addressing specifies the index of a register where the value of interest is located: A immediate addressing B pseudo-direct addressing C base (or displacement) addressing D register addressing E PC-relative addressing
1. Write an instruction sequence to save the current content of the flag in memory location MEM1 and then reload the flags with the contents of memory location MEM2. LAHF MOV MEM1, AH MOV AH, MEM2 SAHF HLT 2. Verify the operation of the following instructions that affect carry flag, start with CF = 0. CLC STC СМС 3. Write an instruction sequence to configure the 8086 as follows: Interrupts not accepted; Save the original contents of flag SF,ZF,AF,PF and CF at the address [0700H], then Clear the carry.
6. What is the address of executing the following instruction: MOV CX, [FEH] if you know that DS= DC00H? OCL: DCOFEH, CH: DCOFFH OCL: DCFEH, CH: DCFFH CL: DCFFH, CH: DCFFH CL: DCOFFH, CH: DCOFFH
need this one