8.3 An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2's complement data. Do the following: LD address IIAcc - Memory [address], read from LM2 IIAcc - data (a 2's complement number, sign extended) IIAcc - Acc + data (data is a 2's complement number, sign extended) IIACC - Acc - data (data is a 2's complement number, sign extended) IIAcc - Acc + Memory[address] I/M[address] - Acc IIACC - Acc - Memory[address] I/PP - address LD data ADD data SUB data ADD (address) STM (address) SUB (address) JMP address JZ address a) Draw a data path for the CPU assuming the DM has separate input and output bus as in the data path shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (40 pts)
8.3 An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2's complement data. Do the following: LD address IIAcc - Memory [address], read from LM2 IIAcc - data (a 2's complement number, sign extended) IIAcc - Acc + data (data is a 2's complement number, sign extended) IIACC - Acc - data (data is a 2's complement number, sign extended) IIAcc - Acc + Memory[address] I/M[address] - Acc IIACC - Acc - Memory[address] I/PP - address LD data ADD data SUB data ADD (address) STM (address) SUB (address) JMP address JZ address a) Draw a data path for the CPU assuming the DM has separate input and output bus as in the data path shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (40 pts)
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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![8.3 An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2's
complement data. Do the following:
LD address
IIAcc - Memory [address], read from LM2
IIAcc - data (a 2's complement number, sign extended)
IIAcc - Acc + data (data is a 2's complement number, sign extended)
IIAcc - Acc - data (data is a 2's complement number, sign extended)
IIAc-
LD data
ADD data
SUB data
ADD (address)
STM (address)
SUB (address)
JMP address
Acc + Memory[address]
IIM[address] - Acc
IIAcc - Acc - Memory[address]
//PP - address
JZ address
a) Draw a data path for the CPU assuming the DM has separate input and output bus as in the data
path shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (40 pts)](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F88d679bb-6151-4f24-a6e8-f69c82177d1d%2F55c9241b-8703-4d53-8f51-5af290f243ec%2Frq312eq_processed.png&w=3840&q=75)
Transcribed Image Text:8.3 An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2's
complement data. Do the following:
LD address
IIAcc - Memory [address], read from LM2
IIAcc - data (a 2's complement number, sign extended)
IIAcc - Acc + data (data is a 2's complement number, sign extended)
IIAcc - Acc - data (data is a 2's complement number, sign extended)
IIAc-
LD data
ADD data
SUB data
ADD (address)
STM (address)
SUB (address)
JMP address
Acc + Memory[address]
IIM[address] - Acc
IIAcc - Acc - Memory[address]
//PP - address
JZ address
a) Draw a data path for the CPU assuming the DM has separate input and output bus as in the data
path shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (40 pts)
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