8.13. A 1-T cell memory can be fabricated using PMOS transistors in the array shown in Fig. 8.46. (a) What are the voltages stored on the capacitor corres- ponding to logic 0 and 1 levels for a technology

8.13. A 1-T cell memory can be fabricated using PMOS transistors in the array shown in Fig. 8.46. (a) What are the voltages stored on the capacitor corres- ponding to logic 0 and 1 levels for a technology

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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Question

100%

Use K = 25 μA/V², K₂ = 10 µA/V², VTN = 1 V₂
and VTP = -1 V unless otherwise indicated. For
simulation purposes, use the values in Appendix B.
8.13. A 1-T cell memory can be fabricated using PMOS
transistors in the array shown in Fig. 8.46. (a) What
are the voltages stored on the capacitor corres-
ponding to logic 0 and 1 levels for a technology
using VDD = 5 V? (b) Repeat for VDD = 3 V.
VDD
BL
Cc
Ţ
WL
Figure 8.46

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