1. The logic symbol, truth table of 2-4 decoder and its Verilog code is shown in Fig 1(a). Nowplease fill the following blanks to complete the Verilog code design of 3-8 decoder according to itslogic symbol and truth table shown in Fig 1(b).74x138G1OG2AOG2BABC2-to-4decoderAOA1ENYO OY1 OY2 OY3 OY4 OY5 OY6 OY7 OYOY1Y2Y3always (A0, A1, EN)if (EN==1)(Y3, Y2, Y1, YO} = 4'b0000;elsecase ((A1,A0})endmoduleInputsG1 G2A L G2B_L0Xmodule Vr2to4dec_b1(A0, A1, EN, YO, Y1, Y2, Y3);input A0, A1, EN;output reg YO, Y1, Y2, Y3;X111111112'b00: {Y3,Y2, Y1, YO} = 4'b0001;2'b01: {Y3,Y2, Y1, YO} = 4'b0010;2'b10: (Y3, Y2, Y1, YO) = 4'b0100;2'b11: {Y3, Y2, Y1, YO) = 4'b1000;default: (Y3, Y2, Y1, YO} = 4'b0000;endcaseX1X00000000XX100000000module Vr3to8dec (inputoutput regalways @ (*) beginif ({G1, G2A, G2B}!=3'b100)сXXXEN A10111100001111InputsBXXFig 1(a)X0011XAXXX00110011Fig 1(b)0101A001X010101Y7 L11111111110Y300001Y6_L Y5_L1111111111101111111011OutputsY20001Y10Y4_L1111111011101Outputs0000);Y3_L Y2_L1111111011111YO010100111111Y1_L111101111YO_L1110111111 else case(deault:endcaseendendmodule

Answered: Image /qna-images/answer/0eec967a-ac6e-4859-a1e7-ed7946ecf76c.jpg

74x138 G1 OG2A OG2B A B C YO O Y1 O Y2 O Y3 O Y4 O Y5 O Y6 O Y7 O G1 0 X X 1 1 1 1 1 1 1 1 Inputs G2A_L G2B L X 1 X 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 module Vr3to8dec ( input output reg always @ (*) begin if ({G1, G2A, G2B}!=3'b100) с X X X Fig 1(a) B A X X X X X X 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Fig 1(b) 1 0 1 0 1 0 1 Y7_L Y6_L Y5_L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 Outputs Y4_L Y3_L Y2_L Y1_L YO_L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 ); 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

74x138 G1 OG2A OG2B A B C YO O Y1 O Y2 O Y3 O Y4 O Y5 O Y6 O Y7 O G1 0 X X 1 1 1 1 1 1 1 1 Inputs G2A_L G2B L X 1 X 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 module Vr3to8dec ( input output reg always @ (*) begin if ({G1, G2A, G2B}!=3'b100) с X X X Fig 1(a) B A X X X X X X 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Fig 1(b) 1 0 1 0 1 0 1 Y7_L Y6_L Y5_L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 Outputs Y4_L Y3_L Y2_L Y1_L YO_L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 ); 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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Question

1. The logic symbol, truth table of 2-4 decoder and its Verilog code is shown in Fig 1(a). Now
please fill the following blanks to complete the Verilog code design of 3-8 decoder according to its
logic symbol and truth table shown in Fig 1(b).
74x138
G1
OG2A
OG2B
A
B
C
2-to-4
decoder
AO
A1
EN
YO O
Y1 O
Y2 O
Y3 O
Y4 O
Y5 O
Y6 O
Y7 O
YO
Y1
Y2
Y3
always (A0, A1, EN)
if (EN==1)
(Y3, Y2, Y1, YO} = 4'b0000;
else
case ((A1,A0})
endmodule
Inputs
G1 G2A L G2B_L
0
X
module Vr2to4dec_b1(A0, A1, EN, YO, Y1, Y2, Y3);
input A0, A1, EN;
output reg YO, Y1, Y2, Y3;
X
1
1
1
1
1
1
1
1
2'b00: {Y3,Y2, Y1, YO} = 4'b0001;
2'b01: {Y3,Y2, Y1, YO} = 4'b0010;
2'b10: (Y3, Y2, Y1, YO) = 4'b0100;
2'b11: {Y3, Y2, Y1, YO) = 4'b1000;
default: (Y3, Y2, Y1, YO} = 4'b0000;
endcase
X
1
X
0
0
0
0
0
0
0
0
X
X
1
0
0
0
0
0
0
0
0
module Vr3to8dec (
input
output reg
always @ (*) begin
if ({G1, G2A, G2B}!=3'b100)
с
X
X
X
EN A1
0
1
1
1
1
0
0
0
0
1
1
1
1
Inputs
B
X
X
Fig 1(a)
X
0
0
1
1
X
A
X
X
X
0
0
1
1
0
0
1
1
Fig 1(b)
0
1
0
1
A0
0
1
X
0
1
0
1
0
1
Y7 L
1
1
1
1
1
1
1
1
1
1
0
Y3
0
0
0
0
1
Y6_L Y5_L
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
Outputs
Y2
0
0
0
1
Y1
0
Y4_L
1
1
1
1
1
1
1
0
1
1
1
0
1
Outputs
0
000
);
Y3_L Y2_L
1
1
1
1
1
1
1
0
1
1
1
1
1
YO
0
1
0
1
0
0
1
1
1
1
1
1
Y1_L
1
1
1
1
0
1
1
1
1
YO_L
1
1
1
0
1
1
1
1
1
1

else case(
deault:
endcase
end
endmodule

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