DO NOT USE nor, li, etc....ONLY USE RISC-V assembly code (only use instructions from pictures below) 6.Comment on each snippet with what the snippet does. Assume that there is anarray, int arr [6] = (3, 1, 4, 1, 5, 9}, which starts at memory address0xBFFFFF00. You may assume that each integer is stored in 4 bytes. Register a0 containsarr's address 0xBFFFFF00.a)b)1w1waddSWloop:end:to, 0 (a0)t1, 8 (20)t2, to, t1t2, 4 (a0)addsltibeqslliadd1wsubSWaddijto, x0, x0t1, to, 6t1, x0, endt2, to, 2t3, a0, t2t4, 0 (t3)t4, x0, t4t4,0 (t3)to, to, 1loop RISC-V RV321 Instructions SubsetR-type InstructionsALU performs the required operations on two source registers (rs1 and rs2) and stores ALU result back to thedestination register rd.I-type ALU InstructionsALU performs the required operations on the source register rs1 and immediate constant, and stores the ALU resultback to the destination register rd.CategoryArithmeticLogicalTABLE 3.5 Basic Identities of Boolean AlgebraShiftInstructionAddSubtractAdd immediateSet less thanSet less than immediateSet less than unsignedSet less than immediate, unsignedAndInclusive orExclusive orAnd immediateInclusive or immediateExclusive or immediateShift left logicalShift right logicalShift right arithmeticShift left logical immediateShift right logical immediateShift right arithmetic immediateExampleadd x5, x6, x7sub x5, x6, x7addi x5, x6, 20slt x5, x6, x7slti x5, x6, 20sltu x5, x6, x7sltiu x5, x6, 20and x5, x6, x7or x5, x6, x8xor x5, x6, x9andi x5, x6, 20ori x5, x6, 20xori x5, x6, 20sll x5, x6, x7srl x5, x6, x7sra x5, x6, x7slli x5, x6, 3srli x5, x6, 3srai x5, x6, 3Meaningx5 = x6 +x7x5 = x6 - x7x5 = x6 + 20x5 = x6 < x7x5 = x6 < 20x5 = x6 <₁ x7x5 = x6 <₁ 20x5 = x6 & x7x5 = x6 | x8x5 = x6 ^ x9x5 = x6 & 20x5 = x6 | 20x5 = x6 ^ 20x5 = x6 << x7x5 = x6 >> x7x5 = x6 >> x7x5 = x6 << 3x5 = x6 >> 3x5 = x6 >> 3CommentsThree register operands; addThree register operands; subtractUsed to add constantsUsed to compare two registers as 2's complement numbersUsed to compare a register to a constant as 2's complement numbersUsed to compare two registers as unsigned numbersUsed to compare a register to a constant as unsigned numbersThree register operands; bit-by-bit ANDThree register operands; bit-by-bit ORThree register operands; bit-by-bit XORBit-by-bit AND register with constantBit-by-bit OR register with constantBit-by-bit XOE register with constantShift left by registerShift right by registerArithmetic shift right by registerShift left by immediateShift right by immediateArithmetic shift right by immediateData TransferMemory Read (I-type Instructions)Read memory at address (Reg [rsl] + offset) and store to the destination register rd.Memory Write (S-type Instructions)Write register content (Reg [rs2]) to memory at address (Reg [rs1] + offset).CategoryData TransferInstructionluiInstructionExamplelb x5, 40(x6)Ibu x5, 40(x6)Ih x5, 40(x6)Ihu x5, 40(x6)Store byteIw x5, 40(x6)sb x5, 40(x6)sh x5, 40(x6)sw x5, 40(x6)Store halfwordStore wordLoad upper immediatelui x5, 0x12345Add upper immediate to PC auipc x5, 0x12345CategoryLoad byteLoad byte, unsignedLoad halfwordConditionalbranchLoad halfword, unsignedLoad wordU-Type InstructionsLui: load upper immediate instruction which load 20-bit immediate constant from the instruction and storeto the upper 20 bits of the destination register rd.x5, 0xAC516x5= 0xAC516000MeaningInstructionBranch if equalBranch if not equalBranch if less thanBranch if greater orequalBranch if less, unsignedBranch if greater orequal, unsignedUnconditional Jump and linkbranchJump and link registerMeaningx5 = Memory [x6+40]x5 = Memory [x6+40]x5 = Memory [x6 + 40]x5 = Memory [x6+40]x5 = Memory [x6 + 40]Memory[x6 +40] = x5Memory[x6 +40] = x5Memory[x6 + 40] = x5x50x12345000x5 PC + 0x12345000Examplebeq x5, x6, 100bne x5, x6, 100blt x5, x6, 100bge x5, x6, 100Branch Instructions (B-type and J-type)Conditional branch instructions: B-type (if branch condition is true, then go to label; otherwise continue to the nextinstruction after the branch instruction)Unconditional branch instructions: J-type (used for function calls and returns, these two instructions are used as apair.bltu x5, x6, 100bgeu x5, x6, 100Byte from memory to registerUnsigned byte from memory to registerHalfword from memory to registerUnsigned halfword from memory to registerWord from memory to registerByte from register to memoryHalfword from register to memoryWord from register to memoryLoads 20-it constant shifted left 12 bitsUsed for PC-relative data addressingjal x1, 100jalr x1, 100 (x5)CommentsU-Type Format001011010 1100 0101 0001 0110Meaningif (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 > x6) go to PC+100if (x5 x6) go to PC+100if (x5 > x6) go to PC+100x1 = PC+4; go to PC+100x1 = PC+4; go to x5+1000110111CommentsPC-relative branch if registers equalPC-relative branch if registers not equalPC-relative branch if registers lessPC-relative branch if registers greateror equalPC-relative branch if registers less,unsignedPC-relative branch if registers greateror equal, unsignedPC-relative procedure callProcedure return; indirect call

We need to comment on code snippet to find the outcome.

6. Comment on each snippet with what the snippet does. Assume that there is an array, int arr [6] = (3, 1, 4, 1, 5, 9}, which starts at memory address 0xBFFFFF00. You may assume that each integer is stored in 4 bytes. Register a0 contains arr's address 0xBFFFFF00. a) b) 1w 1w add SW loop: end: to, 0 (20) t1, 8 (20) t2, to, t1 t2, 4 (a0) add slti beq slli add 1w sub SW addil j to, x0, x0 t1, to, 6 t1, x0, end t2, to, 2 t3, a0, t2 t4, 0(t3) t4, x0, t4 t4, 0 (t3) to, to, 1 loop

6. Comment on each snippet with what the snippet does. Assume that there is an array, int arr [6] = (3, 1, 4, 1, 5, 9}, which starts at memory address 0xBFFFFF00. You may assume that each integer is stored in 4 bytes. Register a0 contains arr's address 0xBFFFFF00. a) b) 1w 1w add SW loop: end: to, 0 (20) t1, 8 (20) t2, to, t1 t2, 4 (a0) add slti beq slli add 1w sub SW addil j to, x0, x0 t1, to, 6 t1, x0, end t2, to, 2 t3, a0, t2 t4, 0(t3) t4, x0, t4 t4, 0 (t3) to, to, 1 loop

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

DO NOT USE nor, li, etc....ONLY USE RISC-V assembly code (only use instructions from pictures below)

6.
Comment on each snippet with what the snippet does. Assume that there is an
array, int arr [6] = (3, 1, 4, 1, 5, 9}, which starts at memory address
0xBFFFFF00. You may assume that each integer is stored in 4 bytes. Register a0 contains
arr's address 0xBFFFFF00.
a)
b)
1w
1w
add
SW
loop:
end:
to, 0 (a0)
t1, 8 (20)
t2, to, t1
t2, 4 (a0)
add
slti
beq
slli
add
1w
sub
SW
addi
j
to, x0, x0
t1, to, 6
t1, x0, end
t2, to, 2
t3, a0, t2
t4, 0 (t3)
t4, x0, t4
t4,
0 (t3)
to, to, 1
loop

RISC-V RV321 Instructions Subset
R-type Instructions
ALU performs the required operations on two source registers (rs1 and rs2) and stores ALU result back to the
destination register rd.
I-type ALU Instructions
ALU performs the required operations on the source register rs1 and immediate constant, and stores the ALU result
back to the destination register rd.
Category
Arithmetic
Logical
TABLE 3.5 Basic Identities of Boolean Algebra
Shift
Instruction
Add
Subtract
Add immediate
Set less than
Set less than immediate
Set less than unsigned
Set less than immediate, unsigned
And
Inclusive or
Exclusive or
And immediate
Inclusive or immediate
Exclusive or immediate
Shift left logical
Shift right logical
Shift right arithmetic
Shift left logical immediate
Shift right logical immediate
Shift right arithmetic immediate
Example
add x5, x6, x7
sub x5, x6, x7
addi x5, x6, 20
slt x5, x6, x7
slti x5, x6, 20
sltu x5, x6, x7
sltiu x5, x6, 20
and x5, x6, x7
or x5, x6, x8
xor x5, x6, x9
andi x5, x6, 20
ori x5, x6, 20
xori x5, x6, 20
sll x5, x6, x7
srl x5, x6, x7
sra x5, x6, x7
slli x5, x6, 3
srli x5, x6, 3
srai x5, x6, 3
Meaning
x5 = x6 +x7
x5 = x6 - x7
x5 = x6 + 20
x5 = x6 < x7
x5 = x6 < 20
x5 = x6 <₁ x7
x5 = x6 <₁ 20
x5 = x6 & x7
x5 = x6 | x8
x5 = x6 ^ x9
x5 = x6 & 20
x5 = x6 | 20
x5 = x6 ^ 20
x5 = x6 << x7
x5 = x6 >> x7
x5 = x6 >> x7
x5 = x6 << 3
x5 = x6 >> 3
x5 = x6 >> 3
Comments
Three register operands; add
Three register operands; subtract
Used to add constants
Used to compare two registers as 2's complement numbers
Used to compare a register to a constant as 2's complement numbers
Used to compare two registers as unsigned numbers
Used to compare a register to a constant as unsigned numbers
Three register operands; bit-by-bit AND
Three register operands; bit-by-bit OR
Three register operands; bit-by-bit XOR
Bit-by-bit AND register with constant
Bit-by-bit OR register with constant
Bit-by-bit XOE register with constant
Shift left by register
Shift right by register
Arithmetic shift right by register
Shift left by immediate
Shift right by immediate
Arithmetic shift right by immediate
Data Transfer
Memory Read (I-type Instructions)
Read memory at address (Reg [rsl] + offset) and store to the destination register rd.
Memory Write (S-type Instructions)
Write register content (Reg [rs2]) to memory at address (Reg [rs1] + offset).
Category
Data Transfer
Instruction
lui
Instruction
Example
lb x5, 40(x6)
Ibu x5, 40(x6)
Ih x5, 40(x6)
Ihu x5, 40(x6)
Store byte
Iw x5, 40(x6)
sb x5, 40(x6)
sh x5, 40(x6)
sw x5, 40(x6)
Store halfword
Store word
Load upper immediate
lui x5, 0x12345
Add upper immediate to PC auipc x5, 0x12345
Category
Load byte
Load byte, unsigned
Load halfword
Conditional
branch
Load halfword, unsigned
Load word
U-Type Instructions
Lui: load upper immediate instruction which load 20-bit immediate constant from the instruction and store
to the upper 20 bits of the destination register rd.
x5, 0xAC516
x5= 0xAC516000
Meaning
Instruction
Branch if equal
Branch if not equal
Branch if less than
Branch if greater or
equal
Branch if less, unsigned
Branch if greater or
equal, unsigned
Unconditional Jump and link
branch
Jump and link register
Meaning
x5 = Memory [x6+40]
x5 = Memory [x6+40]
x5 = Memory [x6 + 40]
x5 = Memory [x6+40]
x5 = Memory [x6 + 40]
Memory[x6 +40] = x5
Memory[x6 +40] = x5
Memory[x6 + 40] = x5
x50x12345000
x5 PC + 0x12345000
Example
beq x5, x6, 100
bne x5, x6, 100
blt x5, x6, 100
bge x5, x6, 100
Branch Instructions (B-type and J-type)
Conditional branch instructions: B-type (if branch condition is true, then go to label; otherwise continue to the next
instruction after the branch instruction)
Unconditional branch instructions: J-type (used for function calls and returns, these two instructions are used as a
pair.
bltu x5, x6, 100
bgeu x5, x6, 100
Byte from memory to register
Unsigned byte from memory to register
Halfword from memory to register
Unsigned halfword from memory to register
Word from memory to register
Byte from register to memory
Halfword from register to memory
Word from register to memory
Loads 20-it constant shifted left 12 bits
Used for PC-relative data addressing
jal x1, 100
jalr x1, 100 (x5)
Comments
U-Type Format
00101
1010 1100 0101 0001 0110
Meaning
if (x5 x6) go to PC+100
if (x5 x6) go to PC+100
if (x5 x6) go to PC+100
if (x5 > x6) go to PC+100
if (x5 x6) go to PC+100
if (x5 > x6) go to PC+100
x1 = PC+4; go to PC+100
x1 = PC+4; go to x5+100
0110111
Comments
PC-relative branch if registers equal
PC-relative branch if registers not equal
PC-relative branch if registers less
PC-relative branch if registers greater
or equal
PC-relative branch if registers less,
unsigned
PC-relative branch if registers greater
or equal, unsigned
PC-relative procedure call
Procedure return; indirect call

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