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4- Write VHDL descriptions for component that implement the following functions. Note that each component will have inputs A, B, C, and D, and a single output, F1 (or F2, F3). F1(A,B,C,D) = '1' if and only if all inputs (A, B, C, and D) are '1' or all inputs are '0'. F2(A,B,C,D)='1' if and only if two of the inputs = '1'. F3(A,B,C,D)='1' if and only if the number of inputs that = '1' is odd. F1 AB CD 00 01 11 00 01 11 10 AB 10 10 CD 00 00 01 11 10 F2 F3 10 AB 01 11 10 CD 00 01 11 10 00 01 11 10 5- Write a VHDL code for the logic circuits mentioned below: (you should use the Process in each code) a- Out1 in1 and sig1 in1 out1 sigt b- 2-input XOR Gate 6- Write an entity declaration and behavioral architecture for a 2 to 1 multiplexer, with input ports a, b, and Sel (Select), and an output port y. The input and output ports are all single bit. Simulate the model using Xilinx ISE Software to demonstrate correct operation. For this assignment, you should turn in the filled-in Karnaugh maps for the problems above, printouts of your VHDL source code, and printouts of your VHDL simulations showing correct operation for all the required input combinations.

4- Write VHDL descriptions for component that implement the following functions. Note that each component will have inputs A, B, C, and D, and a single output, F1 (or F2, F3). F1(A,B,C,D) = '1' if and only if all inputs (A, B, C, and D) are '1' or all inputs are '0'. F2(A,B,C,D)='1' if and only if two of the inputs = '1'. F3(A,B,C,D)='1' if and only if the number of inputs that = '1' is odd. F1 AB CD 00 01 11 00 01 11 10 AB 10 10 CD 00 00 01 11 10 F2 F3 10 AB 01 11 10 CD 00 01 11 10 00 01 11 10 5- Write a VHDL code for the logic circuits mentioned below: (you should use the Process in each code) a- Out1 in1 and sig1 in1 out1 sigt b- 2-input XOR Gate 6- Write an entity declaration and behavioral architecture for a 2 to 1 multiplexer, with input ports a, b, and Sel (Select), and an output port y. The input and output ports are all single bit. Simulate the model using Xilinx ISE Software to demonstrate correct operation. For this assignment, you should turn in the filled-in Karnaugh maps for the problems above, printouts of your VHDL source code, and printouts of your VHDL simulations showing correct operation for all the required input combinations.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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4- Write VHDL descriptions for component that implement the following functions. Note that each component will have inputs A, B, C, and D, and a single output, F1 (or F2, F3). F1(A,B,C,D) = '1' if and only if all inputs (A, B, C, and D) are '1' or all inputs are '0'. F2(A,B,C,D)='1' if and only if two of the inputs = '1'. F3(A,B,C,D)='1' if and only if the number of inputs that = '1' is odd. F1 AB CD 00 01 11 00 01 11 10 AB 10 10 CD 00 00 01 11 10 F2 F3 10 AB 01 11 10 CD 00 01 11 10 00 01 11 10 5- Write a VHDL code for the logic circuits mentioned below: (you should use the Process in each code) a- Out1 in1 and sig1 in1 out1 sigt b- 2-input XOR Gate 6- Write an entity declaration and behavioral architecture for a 2 to 1 multiplexer, with input ports a, b, and Sel (Select), and an output port y. The input and output ports are all single bit. Simulate the model using Xilinx ISE Software to demonstrate correct operation. For this assignment, you should turn in the filled-in Karnaugh maps for the problems above, printouts of your VHDL source code, and printouts of your VHDL simulations showing correct operation for all the required input combinations.
Transcribed Image Text:4- Write VHDL descriptions for component that implement the following functions. Note that each component will have inputs A, B, C, and D, and a single output, F1 (or F2, F3). F1(A,B,C,D) = '1' if and only if all inputs (A, B, C, and D) are '1' or all inputs are '0'. F2(A,B,C,D)='1' if and only if two of the inputs = '1'. F3(A,B,C,D)='1' if and only if the number of inputs that = '1' is odd. F1 AB CD 00 01 11 00 01 11 10 AB 10 10 CD 00 00 01 11 10 F2 F3 10 AB 01 11 10 CD 00 01 11 10 00 01 11 10 5- Write a VHDL code for the logic circuits mentioned below: (you should use the Process in each code) a- Out1 in1 and sig1 in1 out1 sigt b- 2-input XOR Gate 6- Write an entity declaration and behavioral architecture for a 2 to 1 multiplexer, with input ports a, b, and Sel (Select), and an output port y. The input and output ports are all single bit. Simulate the model using Xilinx ISE Software to demonstrate correct operation. For this assignment, you should turn in the filled-in Karnaugh maps for the problems above, printouts of your VHDL source code, and printouts of your VHDL simulations showing correct operation for all the required input combinations.
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