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3. A timing diagram giving the S and R inputs for a NOR-gate S-R latch is shown below, and the NOR-gate circuit is also shown for reference (QN = Q'). a) Fill in the outputs Q and Q, starting with Q = 0 and Q' = 1. Assume the changes happen instantaneously, i.e., ignore any propagation delays in the circuit. R R Q' -QN S b) Repeat the problem, but this time include propagation delays through the circuit. The propagation delay of each NOR gate is 10 ns, and each time division in the figure is also 10 ns. Be careful, and include the different paths through the circuit!

3. A timing diagram giving the S and R inputs for a NOR-gate S-R latch is shown below, and the NOR-gate circuit is also shown for reference (QN = Q'). a) Fill in the outputs Q and Q, starting with Q = 0 and Q' = 1. Assume the changes happen instantaneously, i.e., ignore any propagation delays in the circuit. R R Q' -QN S b) Repeat the problem, but this time include propagation delays through the circuit. The propagation delay of each NOR gate is 10 ns, and each time division in the figure is also 10 ns. Be careful, and include the different paths through the circuit!

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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I have figured out part a. I just am a little confused on how to add the 10ns propagation delay. Do I just scale each line to 10 ns?

thanks for the help

A Trut O ECE M Inbe Ь Ans b Ans | b Ans | Ь Ans | b My | + Pro O Prio Intro MTI O Finc Cha P Das -> A https://d2l.pdx.edu/d2l/le/content/876966/viewContent/5903059/View Update : Q ↑V + Automatic Zoom >> 2 of 3 3. A timing diagram giving the S and R inputs for a NOR-gate S-R latch is shown below, and the NOR-gate circuit is also shown for reference (QN = Q'). a) Fill in the outputs Q and Q', starting with Q = 0 and Q' = 1. Assume the changes happen instantaneously, i.e., ignore any propagation delays in the circuit. R R. Q QN Q' b) Repeat the problem, but this time include propagation delays through the circuit. The propagation delay of each NOR gate is 10 ns, and each time division in the figure is also 10 ns. Be careful, and include the different paths through the circuit! R. 4:32 PM O Type here to search 28% 53°F 12/1/2021 2
Transcribed Image Text:A Trut O ECE M Inbe Ь Ans b Ans | b Ans | Ь Ans | b My | + Pro O Prio Intro MTI O Finc Cha P Das -> A https://d2l.pdx.edu/d2l/le/content/876966/viewContent/5903059/View Update : Q ↑V + Automatic Zoom >> 2 of 3 3. A timing diagram giving the S and R inputs for a NOR-gate S-R latch is shown below, and the NOR-gate circuit is also shown for reference (QN = Q'). a) Fill in the outputs Q and Q', starting with Q = 0 and Q' = 1. Assume the changes happen instantaneously, i.e., ignore any propagation delays in the circuit. R R. Q QN Q' b) Repeat the problem, but this time include propagation delays through the circuit. The propagation delay of each NOR gate is 10 ns, and each time division in the figure is also 10 ns. Be careful, and include the different paths through the circuit! R. 4:32 PM O Type here to search 28% 53°F 12/1/2021 2
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