3) In the circuit shown in Figure 2, assuming ideal op amp properties and no loading effects, answer the following: a) What is the gain of stage 1,Av1 = ? b) What is the gain of stage 2, Av2 = ? Va c) What is the overall gain Av = Von V₁ C1 www R2 FIS ww Stage 1,1 Figure 2 Circuit for question 4 R₂ = 100 kn, C₁ = 16 nF, design R3 and R4 such that Vi R1 R3 www R4 d) Using the following R₁ = 10 kn, input V₂ (t) = 1.0 sin (2π 72 t) [V] has an output amplitude of 12[V]. Stage 2 Vo
3) In the circuit shown in Figure 2, assuming ideal op amp properties and no loading effects, answer the following: a) What is the gain of stage 1,Av1 = ? b) What is the gain of stage 2, Av2 = ? Va c) What is the overall gain Av = Von V₁ C1 www R2 FIS ww Stage 1,1 Figure 2 Circuit for question 4 R₂ = 100 kn, C₁ = 16 nF, design R3 and R4 such that Vi R1 R3 www R4 d) Using the following R₁ = 10 kn, input V₂ (t) = 1.0 sin (2π 72 t) [V] has an output amplitude of 12[V]. Stage 2 Vo
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Question
![3) In the circuit shown in Figure
2, assuming ideal op amp
properties and no loading
effects, answer the following:
a) What is the gain of stage
1, Av₁ = Van
V₁
b) What is the gain of stage
2, A₂₂ = Von
Va
c) What is the overall gain
A₂ = Vo
Vi
d) Using the following R₁ = 10
10
input V₂ (t) = 1.0 sin (2n
.
Vi
C1
R2
FLE
Va
R3
Stage 1
kn, R₂
R2
ΚΩ,
www
R1
+
www
R4
Stage 2
Vo
Figure 2 Circuit for question 4
= 100 ΚΩ, C1 16 nF, design R3 and R4 such that
72-t) [V] has an output amplitude of 12[V].](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Feedd517e-4dd6-494e-b573-27275b1af98e%2Fb4de7076-c8c8-4510-bf60-1d5e31eef45d%2F8gcjavu_processed.jpeg&w=3840&q=75)
Transcribed Image Text:3) In the circuit shown in Figure
2, assuming ideal op amp
properties and no loading
effects, answer the following:
a) What is the gain of stage
1, Av₁ = Van
V₁
b) What is the gain of stage
2, A₂₂ = Von
Va
c) What is the overall gain
A₂ = Vo
Vi
d) Using the following R₁ = 10
10
input V₂ (t) = 1.0 sin (2n
.
Vi
C1
R2
FLE
Va
R3
Stage 1
kn, R₂
R2
ΚΩ,
www
R1
+
www
R4
Stage 2
Vo
Figure 2 Circuit for question 4
= 100 ΚΩ, C1 16 nF, design R3 and R4 such that
72-t) [V] has an output amplitude of 12[V].
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