2- Design Asynchronous counter using positive edge J-K flip flop to count the following states (3→4>5→6→7→8→9→10). Draw the output wave form of the counter.
Given that Design a Asynchronous counter using positive edge J-K flipflop to count the following states that is 3,4,5,9,10,11,12,13,14,15
Then we have to follow some rules
In jk flip flop there is a preset and clear inputs .
They are very useful in this type of counter design
properties of preset (active low)
that is when preset is 0 Then it set the JK flipflop output to 1
when preset is 1 then jk flipflop works normally based on inputs because we take active low preset
properties of clear (active low)'
That is when we 0 to clear then it is active and it set the JK flipflop output to 0
when clear is 1 then JK flipflop works normally based on inputs because we take active low clear
from the given we have to start our initial state at 3 that is 0011
Normally our counter starts from 0000 then we connect this 0000 to inverters and then connect to a Four Input NAND gate and we set our initial count starts from 0011
i will explain in the figure below observe thee figure
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