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2) Design a 2-to-1 multiplexer in which the inputs and outputs consist of single bits. Provide the truth table for this multiplexer using INO and IN1 for the two inputs, S for the select line and OUT for the output. Obtain the minimal standard sum-of-products expression for the output.

2) Design a 2-to-1 multiplexer in which the inputs and outputs consist of single bits. Provide the truth table for this multiplexer using INO and IN1 for the two inputs, S for the select line and OUT for the output. Obtain the minimal standard sum-of-products expression for the output.

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2) Design a 2-to-1 multiplexer in which the inputs and outputs consist of single bits. Provide the truth table for this multiplexer using INO and IN1 for the two inputs, S for the select line and OUT for the output. Obtain the minimal standard sum-of-products expression for the output. 3) Obtain the schematic diagram for the mux designed in 2). Use proper conventions as to the labelling of part numbers, instance numbers and pin numbers. 4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use INO_1, INO_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the outputs. Obtain the schematic diagram for a possible implementation of such a mux following the example given in Figure 3.3 5) Obtain a implementation of a half-adder circuit using standard gates such as AND, OR, NOT, XOR, etc. Obtain the minimal standard sum-of-products expressions for the Carry and Sum out- puts of a half-adder. Compare these expressions with your implementation.
Transcribed Image Text:2) Design a 2-to-1 multiplexer in which the inputs and outputs consist of single bits. Provide the truth table for this multiplexer using INO and IN1 for the two inputs, S for the select line and OUT for the output. Obtain the minimal standard sum-of-products expression for the output. 3) Obtain the schematic diagram for the mux designed in 2). Use proper conventions as to the labelling of part numbers, instance numbers and pin numbers. 4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use INO_1, INO_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the outputs. Obtain the schematic diagram for a possible implementation of such a mux following the example given in Figure 3.3 5) Obtain a implementation of a half-adder circuit using standard gates such as AND, OR, NOT, XOR, etc. Obtain the minimal standard sum-of-products expressions for the Carry and Sum out- puts of a half-adder. Compare these expressions with your implementation.
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