1:58 Homework3 S24_2f933c35f786ea... Done Please attempt all problems below. Half of your grade for this assignment will be based on completion of all problems, the other half of the grade will be based on your score on 2 randomly selected problems. 1. Please note that the switches are connected opposite to what you have seen in class. Thus, when a switch is open, a logic one is recorded, and when the switch is closed, a logic zero is recorded. In addition to the paragraph below, the company has also requested that the circuit be implemented on an FPGA. Please write a Verilog pseudo-code module that will implement your design. Note: pseudo- code only needs to contain the main components of the program, i.e., I inputs, outputs, assignment statements, etc. +5V SW1 -5V SW2 SW3 Logic Circuit •5V →F x5V SW1 and SW2 cannot be closed at the same time. SW3 and SW4. cannot be closed at the same time. F is high if two or more switches are pressed. Additional space is provided for solving problem 1. ୪ ឃ

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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1:58
Homework3 S24_2f933c35f786ea...
Done
Please attempt all problems below. Half of your grade for this assignment will be based on completion
of all problems, the other half of the grade will be based on your score on 2 randomly selected
problems.
1. Please note that the switches are connected opposite to what you have seen in class. Thus, when a
switch is open, a logic one is recorded, and when the switch is closed, a logic zero is recorded. In
addition to the paragraph below, the company has also requested that the circuit be implemented on
an FPGA. Please write a Verilog pseudo-code module that will implement your design. Note: pseudo-
code only needs to contain the main components of the program, i.e., I inputs, outputs, assignment
statements, etc.
+5V
SW1
-5V
SW2
SW3
Logic
Circuit
•5V
→F
x5V
SW1 and SW2 cannot be closed at the
same time. SW3 and SW4. cannot be
closed at the same time. F is high if
two or more switches are pressed.
Additional space is provided for solving problem 1.
୪
ឃ
Transcribed Image Text:1:58 Homework3 S24_2f933c35f786ea... Done Please attempt all problems below. Half of your grade for this assignment will be based on completion of all problems, the other half of the grade will be based on your score on 2 randomly selected problems. 1. Please note that the switches are connected opposite to what you have seen in class. Thus, when a switch is open, a logic one is recorded, and when the switch is closed, a logic zero is recorded. In addition to the paragraph below, the company has also requested that the circuit be implemented on an FPGA. Please write a Verilog pseudo-code module that will implement your design. Note: pseudo- code only needs to contain the main components of the program, i.e., I inputs, outputs, assignment statements, etc. +5V SW1 -5V SW2 SW3 Logic Circuit •5V →F x5V SW1 and SW2 cannot be closed at the same time. SW3 and SW4. cannot be closed at the same time. F is high if two or more switches are pressed. Additional space is provided for solving problem 1. ୪ ឃ
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