12. You want to generate three 50% duty cycle clock signals, each shifted in time by one clock pulse. What circuit would you use? O a binary counter O a twisted-ring counter a decade counter O a modulo-7 counter 13. Which SR-latch circuit has active high inputs? O NAND-type O NOR-type 14. A counter has the count sequence 1, 2, 9, 63, 22, 147, 0, 5, 1, 2, 9, .... How many FFs are required? 06 08 09 O 11 15. One of your fellow students says "All outputs of a synchronous binary counter have a 50% duty cycle". Do you agree? O Yes, I agree O No, I don't agree 16. A 12.0 MHz clock is high for 40 ns. What is the approximate duty cycle? O 39% O 40% O 45% O 48%

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Up-down counter

In digital logic and computing, a counter is a device that stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock. A sequential digital logic circuit is the most common type with an input line or clock and multiple output lines. In the binary or binary-coded decimal (BCD) number system, the values on the input line represents a number by several flip-flops connected in a cascaded manner. They are manufactured as separate integrated circuits and are widely used components in digital circuits. These are also a part of larger integrated circuits. These are a specific type of sequential circuit like registers or the value of the flip-flops serving as the output.