1. What is the difference (or differences) between a TLB and on-chip cache? a. The TLB is direct-mapped, while caches are set associative. b. The TLB is indexed by the virtual address, while caches are Indexed by the physical address. c. The TLB stores virtual-to-physical address transiations, while caches store data. d. The TLB can be slow, but caches need to be fast. e. The TLB stores instructions, while caches store data. 2. Say we have two mutexes, implemented with binary semaphores, and two threads which access them. Which of the following can cause deadlock. a. The threads lock the mutexes in the same order. b. The threads lock the mutexes in a different order. C. The threads unlock the mutexes in the same order. d. The threads uniock the mutexes in a different order.

1. What is the difference (or differences) between a TLB and on-chip cache? a. The TLB is direct-mapped, while caches are set associative. b. The TLB is indexed by the virtual address, while caches are Indexed by the physical address. c. The TLB stores virtual-to-physical address transiations, while caches store data. d. The TLB can be slow, but caches need to be fast. e. The TLB stores instructions, while caches store data. 2. Say we have two mutexes, implemented with binary semaphores, and two threads which access them. Which of the following can cause deadlock. a. The threads lock the mutexes in the same order. b. The threads lock the mutexes in a different order. C. The threads unlock the mutexes in the same order. d. The threads uniock the mutexes in a different order.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
Assume a cache of 1 MB organized as 32 bytes each line. The main memory is 256 MB. a. Determine the number of blocks in main memory b. Determine how to split the address (s-r, r, w) for direct mapping. c. Determine how to split the address (s, w) for associative mapping. d. Determine how to split the address (s-d, d, w) for set-associative each cache set is 4 lines of the cache.
Answer part d only
QUESTION THREE (4) (a) Explain what is the function of buffer. (b) Give THREE (3) advantages of cache work with the buffer for data transfer. (c) What is "bus-snooping" used for.
QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?
Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?
7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can assume write-through and write-allocate write strategies on write hits and misses respectively. Data Access Sequence Address Data 00 01 11 00 00 10 10 00 00 10 01 00 00 01 00 00 00 11 01 00 00 10 10 00 00 01 11 00 00 10 01 00 00 10 00 00 00 10 10 00 Op. lw lw SW lw SW lw lw SW lw lw hits = misses = 32 642 124 I 00 01 10 11 Direct-Mapped Cache V Tag Data hit rate = miss rate = Memory Address 00 00 10 00 00 00 11 00 00 01 00 00 00 01 01 00 00 01 10 00 00 01 11 00 00 10 00 00 00 10 01 00 00 10 10 00 00 10 11 00 00 11 00 00 00 11 01 00 Data 435 9 47 13 7586 86 43 48 673 4 972 1003