1. An SR flip flop can be implemented by cross coupling two NOR gates. R S Fig 4.1a Circuit diagram SR flip flop R Complete the truth table for the output Q of Fig 4.1a. Q R S 0 0 0 1 S Q Q Fig 4.1b Circuit symbol of an SR flip flop

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1. An SR flip flop can be implemented by cross coupling two NOR gates.
R
S
Fig 4.1a Circuit diagram SR flip flop
Complete the truth table for the output Q of Fig 4.1a.
R
S
Q
0
0
0
1
1
0
1
1
2. A clocked SR flip flop
R
S
R
X
1
1
1
0
S
Q
Q
Fig 4.1b Circuit symbol of an SR flip flop
R
с
S
Q
Q
Fig 4.2a Circuit diagram clocked SR flip flop Fig 4.2b Circuit symbol
Complete the truth table for the output Q of a clocked SR flip flop of Fig 4.2a wherein x in the truth
table indicate that the input is not active.
R
S
C
Q
0
0
0
1
1
0
1
1
X
X
Transcribed Image Text:1. An SR flip flop can be implemented by cross coupling two NOR gates. R S Fig 4.1a Circuit diagram SR flip flop Complete the truth table for the output Q of Fig 4.1a. R S Q 0 0 0 1 1 0 1 1 2. A clocked SR flip flop R S R X 1 1 1 0 S Q Q Fig 4.1b Circuit symbol of an SR flip flop R с S Q Q Fig 4.2a Circuit diagram clocked SR flip flop Fig 4.2b Circuit symbol Complete the truth table for the output Q of a clocked SR flip flop of Fig 4.2a wherein x in the truth table indicate that the input is not active. R S C Q 0 0 0 1 1 0 1 1 X X
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