emt-1250-lab-5a

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CUNY New York City College of Technology *

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1250

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Mechanical Engineering

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Apr 3, 2024

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Emt 1250 Lab 5A Fundamentals Of Digital Systems (New York City College of Technology) Scan to open on Studocu Studocu is not sponsored or endorsed by any college or university Emt 1250 Lab 5A Fundamentals Of Digital Systems (New York City College of Technology) Scan to open on Studocu Studocu is not sponsored or endorsed by any college or university Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
Freedom Titan EMT 1250L-E335 DIGITAL SYSTEMS LAB Experiment #5 Combinational Logic Circuit Minimization Professor C. Davidman Date Performed: Monday October 15th, 2018 Date Due: Monday October 22nd, 2018 Grade: Comments: 1 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
Table of Contents Table of Contents…………..Page 2 Objective…………………..Page 3 Equipment………………….Page 3 Instructions……………………...Page 4 Logic Gates…………………….Page 5 Boolean Equations…………….Page 5 Truth Table…………………….Page 6 Logic Gate Circuit Diagram…...Page 6 Wiring Diagram……………….Page 7 Karnaugh Map…………………Page 8 Wiring Diagrams………………Page 9 Questions and Answers………..Page 10 Conclusion…………………….Page 11 2 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
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Objective This experiment aims to prove that certain techniques can be used to lessen the amount of hardware needed to complete a certain computational task by building a different circuit that will do the same computation. IC Chip pin-outs Equipment: Digital Trainer AND Gate (7408) OR Gate (7432) 3 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
Instructions: 1. Wire and connect the circuit shown below. Write the pin numbers for each gate on the circuit diagram. 2. Create a truth table from the circuit by using the (A, B, C and D) switched on the trainer to enter the input numbers (0000-1111) and write the output result for each input number and call the output (Y1). Have the instructor verify that the output result is correct before continuing. 3. From the verified correct output result in step 2, reduce the circuit to find the MSOP (minimum-sum-of-product) Boolean output expression for (Y1); use Boolean algebra. 4. Have the instructor verify the MSOP circuit to be correct and then connect/wire the circuit and find the output using the A, B, C, D switches to enter the numbers provided on the next page and fill in the output column for (Y2) so you can compare output columns side-by-side. 5. Compare output (Y1) to output (Y2), does (Y1) = (Y2)? If not, check the box, wiring, chips, power, and continue troubleshooting until output (Y1) equals output (Y2). 4 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
Logic Gates: AND Gate:- OR Gate:- Logic/Boolean Expression(s): Y = B’ + C’ + D Boolean Algebra Y’= (A’BCD’)+(ABCD’) Y’=BCD’(A’+A) Y’=BCD’ Y’’=B’C’D’’ Y=B’+C’+D 5 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
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Truth Table: A B C D Y1 Y2 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 6 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
Logic Gate Circuit Diagram: 7 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
Karnaugh Map 8 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
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Wiring Diagram: 9 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
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Questions and Answers Q1: Does (Y1) = (Y2)? Answer with (yes or no). A1: Yes. Q2: If the answer is yes, explain the method used and why they are equal in your report? A2: We used a karnaugh map to minimize and optimize the circuit that we were originally given. The minimized equation was then used to build a new circuit. We then proceeded to test every single combination and the truth table turned out to be the same. 11 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868
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Conclusion: This was a fairly simple and easy lab to complete. However we ran into two major problems, both of which stem from the fact that our lecture is significantly behind the lab. The first problem we ran into was that we couldn't solve Boolean algebra because we haven't even started it in lectures. The other problem was that while I am familiar with K-maps, I can confidently say that our lecture Professor never told us “to always take as large group as we can when coupling” so my map came out wrong. It was Professor Davidman who made the above revelation to me. Thanks to that, I'm absolutely more confident in my ability to draw and solve karnaugh maps. After the K-map, building the reduced circuit was easy and so was the testing. Since we got the same output for both truth tables, then I can say we've successfully completed experiment 5A. 12 Downloaded by Patty (joeyalex2004@gmail.com) lOMoARcPSD|32679868