EECS_140_Lab 7_four_bit_adder

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University of Kansas *

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140

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Electrical Engineering

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Jan 9, 2024

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Lab 7: EECS 140 Four Bit Adder1 Adder with Display Objectives The objective of this laboratory exercise is for you to learn how to use modular design in VHDL to create a real world application by implementing an adder unit into an FPGA chip and display the addition result. You will use Xilinx Vivado software to implement a 4-bit adder circuit. You will then connect the result of the adder to the input of your display drivers (from the previous lab). Finally, you will download the circuit design to the board and will test proper functionality of the circuit. An eight bit slide switch will be used for implementing two 4-bit numbers as inputs, the addition will be outputted on two seven segment displays. Discussion

Click here to view the 4-bit full adder block diagram(better quality) Figure 1: Flow chart for Four bit adder (140 students)

We will also introduce modular design for VHDL . This is a powerful tool to streamline FPGA design, avoid code repetition and enhance portability, re-usability and abstraction. For this lab, you will need to write VHDL modules for three components and then instantiate them in the toplevel.vhd file. Look at examples in the modular VHDL tutorial attached above for syntax and usage. • 1 bit full adder: You will have to edit the bit_full_adder.vhd file to include the expressions for sum and carry out of the 1 bit full adder. • display_driver: You have already done this is the last lab. This component takes in a 4-bit input and outputs 7 bits controlling the 7 segments. • LEDdisplay: This component is used to switch between the outputs of display_driver1 and display_driver2 (refer the block diagram attached above). Your outputs on the 2 seven segments will range from 00 to 1E (00 to E1 for multiplier). Tasks VHDL files Figure 2: Flow chart for Four bit multiplier(141 students)

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Download and Add these source files to your new project project navigator. (Right click->Save link as). Also change the file extension to .vhd. EECS 140 students download file 1-4, 141 students download 1-3 and 5-7. 1. bit_full_adder.vhd 2. display_driver.vhd 3. LEDdisplay.vhd 4. toplevel.vhd 5. multiplier flow chart (Honors) better quality 6. bit_mult.vhd (Honors) 7. toplevel.vhd (Honors) Pre Lab Please answer the following questions and submit to your TA at the start of the lab: 1. (Previous Lab) Why did we have to negate the outputs of the seven segment display? 2. If we wanted the display to light up the left seven segment LEDs instead of the right ones, what would we change? 3. (Current Lab) What's the basic component we will use to implement our 4-bit adder? 4. What kind of 4-bit adder are we designing? 5. What is the significance of the "Anodes" (AN0, AN1, AN2, and AN3) ? Step 1: VHDL Tutorials If you haven't done so yet, review the following tutorials for VHDL and mudular VHDL. Pay special attention the the modular VHDL tutorial, as from now on we will use modular VHDL almost exclusively. • This VHDL tutorial will teach about the VHDL language, its fundamentals, and how to represent a simple circuit in VHDL. • This Modular VHDL tutorial will teach about the using components in VHDL, and creating larger entities by structural design. Step 2: Ripple Carry Adder Design (bit_full_adder.vhd) You should have a good idea of the adder design concept as well as some basic VHDL. The main idea behind thisapproach is to start little, then build big. Hence: * Use the classic truth table, Kmap, Sum-Of-Products approach to get the equations for your outputs (S and Cout). * Edit the bit_full_adder.vhd file with the equations for sum and carry out, that is architecture (Similar to Lab1,2,3).

Step 3: 7 segment displays • You have already worked on display_driver.vhd in the last lab. You do not need to edit this further, just include it in the project . • The file LEDdisplay.vhd is written to switch between 2 of the display_driver's and output the "anodes". This code is provided to you in the VHDL files section. Step 3a: Bit_mult.vhd for 141 Students only • Half adder in the flow chart is nothing but Full adder with Cin => '0' Signal Declaration in bit_mult (141) of signals: s1-s6 (sum signals),c1-c12 (carry signals),a1-a15(and outputs), is already declared, but do go through the syntax and make sure if all are correct. NOTE: Uppercase S represents the multiplier output bits in vector, lowercase signals s1-s6 represents half adder/full adder signals as shown below

Step 4: toplevel.vhd • 140 Students have been provided with parts of this toplevel.vhd file and you need to edit this to declare and port map the missing components. Figure 3a: Bit Multiplier Chart for 4 bit multiplier (141 students)

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Figure 4a: Toplevel Flow Chart for Ripple carry Adder (140 students) This is where you perform component declaration, component instantiation (port mapping) (Details on this is in Lab 7) Signal Declaration in toplevel (140) of signals: s1,s2,s3,s4, c0,c1,c2,c3, sig_segments1,sig_segments2,sig_segments3,sig_segments4 is already declared, but do go through the syntax and make sure if all are correct. Syntax: signal signal_name: std_logic; --for signals which store 1 bit values signal signal_name: std_logic_vector(N downto 0); --for signals which store a vector of bits of length N+1; • Lab 7 tutorial for syntax: Modular VHDL tutorial • Syntax for refering to first bit from a vector SW in VHDL source file is: SW(0) and in contraints file it would be: SW[0] • 141 Students have been provided with parts of this toplevel.vhd file and you need to edit this to declare and port map the missing components. This is where you perform component declaration, component instantiation (port mapping) (Details on this is in Lab 7) Signal Declaration in toplevel (141) of signals: s, sig_segments1,sig_segments2,sig_segments3,sig_segments4 is already declared, but do go through the syntax and make sure if all are correct Syntax: signal signal_name: std_logic; --for signals which store 1 bit values

Figure 4b: Toplevel Flow Chart for 4 bit multiplier (141 students) signal signal_name: std_logic_vector(N downto 0); --for signals which store a vector of bits of length N+1; NOTE: In the above flow chart the clock input (clk) is needed for LEDdisplay as shown in Fig 4a: Toplevel Flow Chart for Ripple carry Adder. NOTE: Port mapping symbol is "=>". Instance name should be different from component name Syntax: Instance_name: Component_name PORT MAP (portname1=> connection1, . . . . portnameN=> connectionN); Instance_name -> user defined name ex: display_driver1 Component_name -> name of the component that is being port mapped, i.e, the name used after key word entity ex: display_driver portname1,portname2.. etc -> are input and output ports of the component being port mapped ex: inputs,seg_out connection1, connection2.. -> are the respective signals/ports of toplevel being connected to the ports of THE component ex: s, sig_segments1 • Lab 7 tutorial for syntax: Modular VHDL tutorial Step 5: XDC file for toplevel You need to create a new XDC file for the toplevel inputs and outputs. You can use any one of the switches as carry_in.

NOTE: All PORTS defined in Toplevel entity should be declared in the contraints file as well. Basys3_Constraints Step 6: Download to the Board Once your toplevel.vhd compiles and generates a bit file, start adept software and program your FPGA as we have done in the earlier labs. Step 7: Evaluate and Correct Now you will want to verify that the board is operating correctly. Change inputs using the slide switches and make sure that you get the correct corresponding output. If you get incorrect outputs retrace your steps making sure you have correct pin assignments and that your VHDL is correct. After you've tested circuit for proper operation, show it to your TA. Lab Report Now write your lab report according the format your TA has outlined for you. Make sure to include into your lab report any possibilities of improvements to your circuits or ways you believe it could have been implemented better.

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