HW7sol

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HW7 Solutions Fall 2023 Prof. Densmore Problem 1 A clock radio can show one of four items: the time, the alarm, the radio station, or the date. These are controlled by two signals s1 and s0 (00 displays the time, 01 the alarm, 10 the station, and 11 the date – assume s1 and s0 control an N-bit mux that passes through the appropriate register). Pressing button X (which sets X=1) sequences the display to the next item. a. Create a state diagram for an FSM for this system. It should have one input bit X and output bits S1 and S0. Be sure to sequence forward by one item each time the button is pressed. In other words be sure to wait for the button to be released before sequencing to the next item. Displaying the time should be the initial state. (4pts) b. Create a truth table for this system. This should include the input, current state, next state, and outputs. (4pts) c. Create the controller circuit diagram for this system. (4pts) current state Inpu t Next state Outpu t C2 C1 C0 X N2 N1 N0 S1 S0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1

HW7 Solutions Fall 2023 Prof. Densmore C2C1\C0 X 00' 01' 11' 10' 00' 0 0 0 0 01' 0 0 1 0 11' 1 1 0 1 10' 1 1 1 1 N2=C2C1’+C2C0’+C2C0X’+C2’C1C0X C2C1\C0 X 00' 01' 11' 10' 00' 0 0 1 0 01' 1 1 0 1 11' 1 1 0 1 10' 0 0 1 0 N1= C1C0’+C1X’+C1’C0X N0=X’ S1=C2 S0=C1 Problem 2 Gray Code FSM a. Draw a state diagram for an FSM with an input G and three outputs x, y, and z. The xyz outputs generate the gray code sequence 000, 010, 011, 001, 101, 111, 110, 100, repeat. The output should change only on a rising clock edge when the input G = 1. Make the initial state 000. (4pts)

HW7 Solutions Fall 2023 Prof. Densmore b. Create a truth table for this system. This should include the input, current state, next state, and outputs. (4pts) current state Inpu t Next state Output C2 C1 C0 G N2 N1 N0 X Y Z 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 c. Create the controller circuit diagram for this system. (4pts) C2C1\C0 G 00' 01' 11' 10' 00' 0 0 1 0 01' 0 0 0 0 11' 1 1 1 1 10' 1 0 1 1 N2=C2C1+C2C0+C1’C0G

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HW7 Solutions Fall 2023 Prof. Densmore C2C1\C0 G 00' 01' 11' 10' 00' 0 1 0 0 01' 1 1 0 1 11' 1 0 1 1 10' 0 0 1 0 N1=C1G’+C2’C0’G+C2C0G C2C1\C0 G 00' 01' 11' 10' 00' 0 0 1 1 01' 0 1 1 1 11' 0 0 0 1 10' 0 0 1 1 N0=C0G’+C1’C0+C2’C1G X=C2 Y=C1 Z=C0 Problem 3 The following FSM has two problems: one state has non-exclusive transitions and another state has incomplete transitions. By ORing and ANDing conditions for each state’s transitions prove that these problems exist. (6pts; 3pts non-exclusive; 3pts incomplete)

HW7 Solutions Fall 2023 Prof. Densmore If we AND each pair of transitions with each other in state A , we get: a * a’b = 0*b = 0 a’b * b’ = a’*0 = 0 a*b’ = ab’, which is not equal to 0. State A’s transitions are thus not exclusive, i.e., both a and b’ could be simultaneously true. ORing state B’s transitions yields: a+a’ = 1 ORing state C’s transitions yields: b Clearly, state C’s transitions are not completely specified, because their ORing doesn’t result in 1. If b is 0, the FSM doesn’t indicate what to do from state C. Problem 4 Fix these problems by refining the FSM, taking your best guess as to what was the FSM creator’s intent. (4pts) We can address both of these problems with the following changes. The designer likely wanted to stay in state A when a is true, and go to B on a’b and go to C on a’b’. The designer likely wanted to stay in state C when b is 0.

HW7 Solutions Fall 2023 Prof. Densmore Problem 5 Please do the following problems from the book (6 th edition numbers given): 5.5 (5pts) Explain the differences among a truth table, a state table, a characteristic table, and an excitation table. Also, explain the difference among a Boolean equation, a state equation, a characteristic equation, and a flip-flop input equation. The truth table describes a combinational circuit. The state table describes a sequential circuit. The characteristic table describes the operation of a flip-flop. The excitation table gives the values of flip-flop inputs for a given state transition. The four equations correspond to the algebraic expression of the four tables . 5.48 (write Verilog; simulate with Verilog IDEs (such as Vivado, EDA Playground); turn in Verilog) (10 pts) Write an HDL model of the Mealy FSM described by the state diagram in Fig. P5.48 . Develop a testbench and demonstrate that the machine state transitions and output correspond to its state diagram. //Assume "a" is the reset state. module Prob_5_48 (output reg y_out, input x_in, clk, reset_b); parameter s_a = 2'd0; parameter s_b = 2'd1; parameter s_c = 2'd2; parameter s_d = 2'd3; reg [1: 0] state, next_state; always @ (posedge clk) if (reset_b == 1'b0) state <= s_a; else state <= next_state; always @ (state, x_in) begin next_state = s_a; y_out = 0; case (state) s_a: if (x_in == 1'b0) begin next_state = s_b; y_out = 1; end else begin next_state = s_c; y_out = 0; end s_b: if (x_in == 1'b0) begin next_state = s_c; y_out = 0; end else begin next_state = s_d; y_out = 1; end s_c: if (x_in == 1'b0) begin next_state = s_b; y_out = 0; end else begin next_state = s_d; y_out = 1; end

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HW7 Solutions Fall 2023 Prof. Densmore s_d: if (x_in == 1'b0) begin next_state = s_c; y_out = 1; end else begin next_state = s_a; y_out = 0; end default: begin next_state = s_a; y_out = 0; end endcase end endmodule Testbench module t_Prob_5_48 (); reg x_in, clk, reset_b; wire y_out; Prob_5_48 M0 (y_out, x_in, clk, reset_b); initial #400 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; #30 reset_b = 1; #30 x_in = 0; #100 reset_b = 0; #110 reset_b = 1; #110 x_in = 1; #200 reset_b = 0; #210 reset_b = 1; #210 x_in = 0; #220 x_in = 1; #300 reset_b = 0; #310 reset_b = 1; #310 x_in = 1; #330 x_in = 0; join endmodule 5.50 (write Verilog; simulate with Verilog IDEs (such as Vivado, EDA Playground); turn in Verilog) (15 pts) – turn in your state diagram as well as a separate file.

HW7 Solutions Fall 2023 Prof. Densmore Asynchronous Moore FSM has a single input, x_in, and a single output y_out. The machine is to monitor the input and remain in its reset state until a second sample of x_in is detected to be 1. Upon detecting the second assertion of x_in y_out is to assert and remain asserted until a fourth assertion of x_in is detected. When the fourth assertion of x_in is detected the machine is to return to its reset state and resume monitoring of x_in. 1. (a) Draw the state diagram of the machine. 2. (b)Write and verify an HDL model of the machine. module Prob_5_50 (output y_out, input x_in, clk, reset_b); parameter s_a = 2'd0; parameter s_b = 2'd1; parameter s_c = 2'd2; reg Set_flag; reg Clr_flag; reg [1:0] state, next_state; assign y_out = (state == s_b) || (state == s_c) ; always @ (posedge clk) if (reset_b == 1'b0) state <= s_a; else state <= next_state; always @ (state, x_in, flag) begin next_state = s_a; Set_flag = 0; Clr_flag = 0;

HW7 Solutions Fall 2023 Prof. Densmore case (state) s_a: if ((x_in == 1'b1) && (flag == 1'b0)) begin next_state = s_a; Set_flag = 1; end else if ((x_in == 1'b1) && (flag == 1'b1)) begin next_state = s_b; Set_flag = 0; end else if (x_in == 1'b0) next_state = s_a; s_b: if (x_in == 1'b0) next_state = s_b; else begin next_state = s_c; Clr_flag = 1; end s_c: if (x_in == 1'b0) next_state = s_c; else next_state = s_a; default: begin next_state = s_a; Clr_flag = 1'b0; Set_flag = 1'b0; end endcase end always @ (posedge clk) if (reset_b == 1'b0) flag <= 0; else if (Set_flag) flag <= 1'b1; else if (Clr_flag) flag <= 1'b0; endmodule Testbench module t_Prob_5_50 (); wire y_out; reg x_in, clk, reset_b; Prob_5_50 M0 (y_out, x_in, clk, reset_b); initial #500 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 1'b0; #20 reset_b = 1; #20 x_in = 1'b0; #40 x_in = 1'b1; #50 x_in = 1'b0; #80 x_in = 1'b1; #100 x_in = 0; #150 x_in = 1'b1; #160 x_in = 1'b0; #200 x_in = 1'b1; #230 reset_b = 1'b0; #250 reset_b = 1'b1; #300 x_in = 1'b0; join endmodule

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