EEL 3307c Lab 3

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Apr 3, 2024

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EEL 3307c Lab 3: Transistor Biasing Joshua Barshay and Lab Partner Ammar Mubarez Results Gathered on 2/7&14/23

1.0 Pre-Lab Results The prelab results can be viewed below: 2.0 Simulations Each of the circuits in the lab manual was simulated for each step of the experimental process described in the experimental procedure section of the lab manual. The first circuit that was simulated was figure 1b with R E =0. The results of the simulation with all required values can be seen below.

The second circuit that was simulated was figure 1b with R E =1.8kOhms. The results of the simulation with all required values can be viewed below. The next circuit that was simulated was figure 3 with the AC source and capacitor removed to calculate the Q point (as per instruction in the lab session). The results of this simulation with the values for the Q point can be seen below.

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Finally the full circuit in figure 3 with the AC source and capacitor was simulated. The circuit diagram followed by the waveform of the node voltage outputs can be viewed below.

(V E in blue, V C in gray, and V CE in green) 3.0 Experimental Procedure and Results Gathered The circuit for figure 1b. was modeled on the breadboard. The resistor values used were those given in the pre-lab and the R E resistor was disconnected. I B , I C , and V CE were all measured (as a note I B refers to the base current, I C refers to the collector current, and V CE refers to the voltage from collector to emitter). The results that were obtained are listed below. I C :

I B : (The picture is a bit blurry but the current is .0138 mA) V CE : The voltage V BB (base bias voltage) was then adjusted so that the collector current was as close to 2 mA as possible. This resulted in an input of about .73 to .74 volts (an exact value was uncertain due to some noise from the DMM). The transistor was then replaced by two different transistor with the same part number and the Collector current was measured.

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1 st transistor: (the picture is a bit blurry but the current is 2.165 mA) 2 nd transistor: 3 rd transistor: (the image is a bit blurry but the value is 2.3278 mA)

The difference in collector current seen by the three different transistors can be explained by the concept of beta. Beta is the value that represents current gain within the transistor. Each transistor has a certain beta value that is caused by the differences in the doping of the semiconductor material. Each of the transistors used in this experiment had slightly different beta values that resulted in slightly different current gain which is likely caused by slight imperfections in the manufacturing process. The value of R E was then changed to 1.8 kOhms and the same measurements were taken again. The results of these measurements can be viewed below. I C : I B :

V CE : Finally the circuit for figure 3 was attached to the breadboard with the AC source and the capacitor removed. The resistor value calculated and used in the circuit creation were R 1 =2kOhms and R 2 =1.2kOhms. The collector current and the transistor voltage were measured. The results can be viewed below. I C :

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V CE : Finally the 20 mV peak-to-peak AC source and 10uf capacitor were attached to the circuit as per figure 3. The voltage from collector to ground (V C ), the voltage from emitter to ground (V E ) and the voltage from collector to emitter (V CE ) were measured. The results can be viewed below. (V IN in yellow V E in orange V C in green and V CE in blue). 4.0 Results Analysis and Calculations For the beta calculations below the formula B=I C /I B was used. For the q point values the q point is listed as (V CE , I C ). The results analysis for figure 1b without R E can be seen below.

Expected Simulated Actual Q point (V, mA) (8.4, 2) (.845, 2.051) (8.26, 2.41) B 220 220.07 174 I C (mA) 2 2.051 2.4132 I B (mA) .00909 .00941 .0138 V BB (That makes I C 2mA) (V) .75 .845 .73 The results obtained in the lab and the results from the pre-lab theory match somewhat but have slight discrepancies as do the simulation results. The simulation software used (NI Multisim) expects the current within the transistor to be dissipated at a rate much greater than what is seen in theory or experimentation. The actual transistor, however, also seemed to have a higher beta value that the supposed 220 that was assumed in the theoretical calculations. This is likely due to slight imperfection in quality control and manufacturing. The results analysis for figure 1b with R E can be seen below. Expected Simulated Actual Q point (V, mA) (4.8, 2) (4.5, 2.02) (4.79, 2.02) B 220 220.02 219.56 I C (mA) 2 2.022 2.02 I B (mA) .00909 .00919 .0092 V BB (That makes I C 2mA) (V) 4.35 4.50 4.35 The expected results matched very closely with the actual results for this step which is good. The largest difference between the theoretical calculations and the actual results was the I B current and the cause of this difference was probably a lack of sensitivity in the DMM used in the lab. The simulation resulted in values with noticeable discrepancies however, as discussed previously, these discrepancies are likely due to how the simulation software deals with current dissipation within the actual transistor. The simulation seems to dissipate more current within the transistor than the ideal model in the expected results and the actual transistor used in the lab. The differences in the I C values of the three transistors from figure 1b without R E can be seen below. 1 st transistor 2 nd transistor 3 rd transistor I C 2.165 2.236 2.327

As was discussed earlier the differing collector current values is likely due to some differences seen by each transistor in the manufacturing process. This could be anything from slight impurities making their way into the silicon during doping to degradation during the packaging and shipping process. The measurements for figure 3 can be viewed below Simulated Actual DC Q point (V, mA) (4.65, 2.03) (4.36, 2.15) V C (V) 3.72 3.67 V E (V) 8.33 8.11 V CE (V) 4.61 4.44 The results obtained in this step show the largest amount of discrepancy. This is likely due to the simulation’s way of dealing with current dissipation within the transistor and how that current dissipation affects the current seen by each resistor in the system and how those currents affect the node voltages measured in the lab. This is supported by the fact that the current seen in the lab was slightly higher than the current seen in simulation. 5.0 Conclusion The overall experiment was a success. The results obtained in experimentation matched very closely with the expected theoretical results. Most of the discrepancies observed were small enough to be considered moot for the purposes of this lab in particular. In a more precise context the discrepancies may be significant but for these purposes they are not. This experiment helped teach how to properly bias BJT NPN resistors in forwards bias mode without damaging the transistor. It also taught how to properly deal with varying beta values and how to calculate a beta value when give the base and collector currents.

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