Homework_7___Circuit_Performance

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Apr 3, 2024

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Name: Collaborators: HW 7: Circuit Performance/FSMs ECE 2322 March 13, 2024 Instructions • This assignment must be turned in electronically, via Canvas, by the deadline. Once the Canvas late period ends, there will be no opportunity to submit the assignment. • Submit your answers to each question in a file called hw7.pdf. Your answers can be submitted on this template or a separate document; however, it is critical that they are easily legible . You should use a word processor or other application to produce your submission, rather than writing it by hand. • You must produce all answers for this assignment by yourself. You may freely consult with TAs or the instructor. You may post questions about the assignment on Piazza. If you believe your question might violate academic integrity guidelines or if you include any of your work in the post, feel make the post private so that it is only visible to instructors. • You may consult with other students in the course about this assignment. If you do, you must list all of their names on the first page . When discussing the assignment with others, keep all discussions about specific problems verbal. Do not write anything or make any permanent notes that are specific to the assignment problems. Performance Analysis Gate Propogation Delay (ps) NOT 15 2-input NAND 20 3-input NAND 30 2-input NOR 30 2-input NOR 45 2-input AND 30 3-input AND 40 2-input OR 40 3-input OR 55 2-input XOR 60 1

HW 7: Circuit Performance/FSMs ECE 2322 March 13, 2024 1. [ 20 points ] Sketch a schematic for a fast 3:8 decoder. Use only the gates listed in the table above. Design your decoder to have the shortest possible critical path . Indicate which path of the circuit is the critical path and how long it is. 2. Consider the circuit above, which computes a registered four-input XOR function. Each two-input XOR gate has a propagation delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has a setup time of 60 ps and a clock-to-Q delay of 70 ps. [ 5 points ] What is the maximum operating frequency of the circuit? [ 10 points ] You can improve the combinational logic to be faster, using the same number and type of gates. Sketch the faster version of the circuit; now what is the maximum operating frequency of this new circuit? 3. For each of the following, compute the task latency , and throughput . 2

HW 7: Circuit Performance/FSMs ECE 2322 March 13, 2024 [ 6 points ] A home baker takes 10 minutes to prepare cake batter and it takes 20 minutes to bake in their oven. They only work on one cake at a time. Latency: min/cake Throughput: cake/min [ 6 points ] To improve performance, the baker buys a second oven and a second mixing bowl and asks a friend to come over and bake at the same time as them. Latency: min/cake Throughput: cake/min [ 3 points ] Is this an example of pipelining? If not, give an example of how one would pipeline baking. [ 8 points ] Consider a pipelined version of the the hierarchical priority encoder from Homework 3, question 7 (pictured above). Assume that the delay of a 2-to-4 priority encoder is 180ps, the delay of a 2-to-1 mux is 50ps and the delay of a 2-input OR gate is 40ps. Each flip-flop has a setup time of 60 ps and a clock-to-Q delay of 70 ps. 3

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HW 7: Circuit Performance/FSMs ECE 2322 March 13, 2024 Latency: ps/operation Throughput: operation/ps [ 2 points ] How could we improve the performance of this pipeline without changing any of the gates used? Finite State Machines 4. [ 20 points ] Describe in words what the above state machine does. Define binary state encodings ( do NOT use a one-hot encoding ), write boolean equations for the next state and output, and sketch a circuit schematic of the FSM. 4

HW 7: Circuit Performance/FSMs ECE 2322 March 13, 2024 5. Design an FSM that takes two inputs, A and B , and generates one output, Z . The output in cycle n, Z n , is either the Boolean AND or OR of the corresponding input A n and the previous input A n − 1 , depending on the other input, B n : Z n = A n A n − 1 if B n = 0 Z n = A n + A n − 1 if B n = 1 [ 3 points ] Is this a Mealy Machine or a Moore machine? [ 17 points ] Sketch the FSM diagram, define binary state encodings ( do NOT use a one-hot encoding ) and write boolean equations for the next state and output. You do not need to draw the circuit schematic. 5