577a hw1

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University of Southern California *

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577A

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Electrical Engineering

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Apr 3, 2024

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1) (12 Points) Short answer questions. a) (2 Points) William Shockley called it “A Magnificent Christmas Gift”? What event was he referring to and in which year was this? It was the first point-contact transistor and was shown to the directors at Bell Labs on 23rd December1947. b) (2 Points) It was an empirical prediction, yet the industry now calls it Moore’s Law. What is the key observation in this law? The number of transistors in a semiconductor chip will approximately double every 24 months. c) (2 Points) What is Dennard Scaling? Dennard scaling is a scaling law that states that as transistors get smaller in successive process nodes the power density stays constant. Based on a 1974 paper co-authored by Robert H. Dennard. d) (2 Points) As we move down in process geometries, there have been a number of ways companies have tried to quantify the process node geometry. Provide two examples of metrics used to quantify the process geometry. The length of the gate and the pitch (or half-pitch) of the metal one layer. e) (2 Points) What do FF, SS, SF,FS, TT process corners represent? Explain. FF: Fast-Fast, SS: Slow-Slow, SF: Slow-Fast, FS: Fast-Slow, TT: Typical. The first letter refers to NMOS and the second letter refers to PMOS. For example, ‘FS’ implies there are global process variations that have resulted in all NMOSs being Faster and all PMOSs being Slower that the nominal (typical) case. Note that process corners induce global variations whereas factors like random dopant fluctuation create local variations. It is more difficult to mitigate local variations as opposed to global variations. f) (2 Points) The EDA (electronic design automation) industry greatly benefited as we followed the path of Moore’s Law with shrinking process nodes. Provide two examples of tools that automated tasks previously done manually/semi-manually. Synthesis tools (from RTL -> gate), Place-and-Route tools, circuit extraction, design-rule-checkers (DRC tools), layout-vs-schematic (LVS) tools.
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