273S23key

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San Jose State University *

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273

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Electrical Engineering

Date

Apr 3, 2024

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Uploaded by ColonelLightning4050

EE273 S’23 midterm A 1. Why are clock timings normally part of drivers and monitors? (10 points) They tend to be implementation specific, and are typically not part of a higher level specific 2. When does verification happen related to design? Why? (10 points) Verification happens before design. Design need to develop an architecture, and then design. They need the verification the moment they have code. 3. Why does uvm_analysis_imp have two parameters? (10 points) One for the message type, and one for the class containing the write function. 4. What are the first two things to look for when planning verification? (10 points) Statically invalid Dynamically invalid Some will say: Customer usage and important features 5. Draw a UVM Box diagram for an observing test bench to check a gray scale communication system. The system uses a 3 bit gray scale code 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 then to 000. The sequence steps forward for each 1 data bit, and steps backward for each 0 data bit. Assume a message is available which has the data to be transmitted. Assume a monitor message is available with the 3 bits of the gray code. The monitor data is sampled every 10ns. You should have at least 5 scoreboard boxes. (30 points) Many solutions: Steps leading to boxes could be: • Detect new code • Check forward one step, or backwards one step • Create one or zero from change • Serial to parallel conversion • Compare to expected 6. Write complete System Verilog code for a uvm_sequence body to generate test patterns for a 32 bit signed adder. Ensure that 250 patterns have A<B, 250 with A negative, and B positive, 250 with A positive and B negative, and 250 with A negative and B negative. Then generate 1000 test patterns with A>B and B is positive. Assume a message data class extended from uvm_sequence_item named ‘SI’ with rand variables A and B. (30 points) Many answers: expecting repeat or for loops containing constrained random cases and start/finish 1 1

EE273 S’23 midterm B 1. If a bus interface is not part of the specification, where should it be handled in UVM? (10 points) Drivers and monitors 2. When does verification happen related to design? Why? (10 points) Verification happens before design. Design need to develop an architecture, and then design. They need the verification the moment they have code. 3. Which UVM components have parameters? Why? (10 points) uvm_sequencer, uvm_driver. uvm_sequence is not a components 4. What are the first two things to look for when planning verification? (10 points) Statically invalid Dynamically invalid Some will say: Customer usage and important features 5. Draw a UVM Box diagram for an observing test bench to check a 7 segment display in a countdown system. The system starts at 80 seconds, and then counts down to 00 seconds. The display is two 7 segment digits. Draw a box diagram for an observing test bench which verifies the display counts down correctly. You receive a monitor message containing 7 segments for 2 digits sampled every 10ns. Your box diagram should have at least 6 scoreboards. (30 points) Many solutions, steps could include: • look for change in 7 segments (2 boxes) • convert 7 segments to digit, record time(2 boxes) • combine two digits into a single number • check time from last digit change • check counts down correctly • check stays at zero 6. Write complete System Verilog code for a uvm_sequence body to generate test patterns for a 32 bit signed multiplier. Ensure that 250 patterns have A equals -B, 250 with A negative, and B positive, 250 with A positive and B negative, and 250 with A negative and B negative. Then generate 1000 test patterns with A>B and B is positive. Assume a message data class extended from uvm_sequence_item named ‘SI’ with rand variables A and B. (30 points) Many answers: expecting repeat or for loops containing constrained random cases and start/finish 2 1

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