Exam2 Spring 2020 v2 solutions

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Apr 3, 2024

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EID: ____________ 1 EE316 – Digital Logic Design Spring 2020 Exam #2 Prof. David Pan and Prof. Nina Telang (TAs: Arkan Abuyazid, Sergio Chacon, Rishabh Sehgal, Mihir Shah, Mertcan Temel, Jerry Yang) UT EID: __________________ Printed Name: _______________________ Your signature is your pledge that you have not and will not cheat on this exam, nor help other students to cheat on this exam. Signature: ______________________ Instructions:  This is an open book and open note exam.  The exam is to be completed in ninety (90) minutes, 7-8:30pm  At 8:30pm, please stop writing, and start to take pictures/scan your solutions, and upload to Gradescope.  Write your UT EID on every page on the top right side.  Show all your work to receive full credit.  State any assumptions you make on your solution (if you feel there is any ambiguity). Problem # 1 ____________/38 Problem # 2 ____________/10 Problem # 3 ____________/15 Problem # 4 ____________/10 Problem # 5 ____________/12 Problem # 6 ____________ /15

EID: ____________ 2 1. [40 points] Answer the following short questions (in the boxes/space provided). a. [4 points] Complete the following table of conversions between decimal to 8-bit 2’s complement binary numbers : Decimal 2’s complement -1 11101111 127 00110011 b. [2 points] [True/False] The LSB of a number and the LSB of its two’s complement are always equal. c. [4 points] Draw the timing diagrams of the three output bits for a divide-by-8 clock. The period of the input clock (shown below) is 100 ns. Also shown are the states/outputs of each state of the FSM used to build this clock divider circuit. d. [2 points] Below is a full subtractor, with single input bits a , b , win (borrow by column on right), and single bit outputs d (difference) and wo (borrow from column on left). For which combination of input bits a and b , is the wo output bit a 1, regardless of the win value. Bit 0 Q 0 Bit 1 Q 1 Bit 2 Q 2 (Q 2 Q 1 Q 0 )

EID: ____________ 3 e. [8 points] Complete the following table which lists the gate delays for each of the circuits listed. Each circuit takes two 4-bit numbers as inputs. Circuit Number of gate delays Ripple carry adder Carry Lookahead adder Ripple borrow subtractor Multiplier – array style f. [6 points] Design, using a strength reduction circuit, a circuit that computes Z=X/3, using only shifts and adds with approximation error < 1% of X. X is a 12- bit input.

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EID: ____________ 4 g. [4 points] Complete the timing diagram below for an 8-bit parallel-load register with 8-bit input I , 8-bit output Q , load control input ld , and synchronous clear input clr . Q h. [4 points] The module below implements a clock divider. What frequency is the output clock (slow_clk) at? Assume the input clock is 80 MHz. module clkdiv(input clk, output reg slow_clk); reg [31:0] count = 0; always @(posedge clk) begin count = count + 1; if(count == 125000) begin slow_clk = ~slow_clk; count = 0; end end endmodule

EID: ____________ 5 i. [4 points] Complete the operation table for the shift register circuit below. S1 S0 Operation 0 0 0 1 1 0 1 1 S1 S0

EID: ____________ 6 2. [10 points] Show how you can implement the function Z (a, b, c, d) = a ʹbd + bʹ c ʹ d ʹ , using two 3-input 2-output lookup tables as shown in the figure below.

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EID: ____________ 7 3. [15 points] Design an ALU with two 8-bit inputs A and B, and control inputs x, y, and z. The ALU should support the operations described in the table below. Use an 8-bit adder and an arithmetic/logic extender. In your design indicate the values/expressions for outputs IA, IB of the AL-extender that will result in the ALU operation. Write logic expressions for IA, IB, Cin. Inputs Operation x y z 0 0 0 S = A - B 0 0 1 S = A + B 0 1 0 S = not(A) 0 1 1 S = A 1 0 0 S = A + 1 1 0 1 S = A - 1 1 1 0 S = A and B (bitwise and) 1 1 1 S = A or B (bitwise or) Inputs IA IB Cin x y z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 IA = IB = Cin =

EID: ____________ 8 4. [10 points] The Cockrell School Diversity and Inclusion Committee is doing some data processing on a recent engineering climate survey. One common method of aggregating data is to take the arithmetic mean of the responses for each respondent. For example, if a survey respondent answered 2, 3, 2, 4 on a 5- point scale for four questions, we can take the average of the responses to generate a score of 2.75 for those four questions for the respondent. The longest group of questions on the survey has eight questions, each on a 5- point scale. Using as few components as possible and the minimum bits necessary for each component to preserve precision, draw a datapath that aggregates the question data for each respondent using the mean method. Round the average to the nearest whole number, e.g., 2.1 will be round up to 2 but 2.5 will be round up to 3. Assume every respondent answered every question.

EID: ____________ 9 5. [12 points] Zoom University has a classroom management system in which it can only either add a person to a class or drop a person from a class one at a time (not simultaneously) when requested by the person. Because the system needs to accomm odate large classes, the system cannot “starve” one group of people, i.e. it cannot keep dropping people until there are no more people to drop, and it cannot keep adding people once the capacity MAX is reach. It keeps track of the current number of people in the class with a counter and displays the number of participants in the class on the screen. Assume add and drop are 1-bit inputs that signal whether there is a person who wants to be added or dropped. Design an HLSM that models the classroom management system. Be sure your HLSM is fully specified.

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EID: ____________ 10 6. [15 points] Design a circuit that calculates letter grades from given point grades out of 100. Assume that there are only 4 letter grades, A, B, C, and D which are connected to four LEDs. When the input grade is greater than or equal to 80, the LED for A should turn on; when it is between 60-79 (inclusive), the LED for B should turn on; when it is between 40-59 (inclusive), the LED for C should turn on; and when it is less than 40, the LED for D should turn on. Use exactly two 7- bit magnitude comparators, one 2-to-1 multiplexer, and one 2-to-4 decoder.