ELEC201 Lab 2

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Feb 20, 2024

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Module 2 Lab – Understanding Basic Logic Gates Thomas Wahl Electrical Engineering Technology, Excelsior University ELEC201: Digital Electronics Dr. Alan Dixon January 21, 2024 1
Module 2 Lab: Understanding Basic Logic Gates Introduction: The objective of this laboratory experiment is to comprehend the functioning of fundamental logic gates through the creation of a truth table using simulation experiments. Run the simulation and use the switch to create input values of 0 and 1. Observe the output in each case and enter the values in the table below. Include a screenshot showing the states of the input and output. Verify that it is a truth table for the inverter: Switch Open A=0 2
Switch Closed A=1 A F 0 1 1 0 Now we will test the AND gate. Draw the test circuit given below in Multisim. Use the generic 2 input AND gate. We will need two switches to test the two inputs: 3
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Run the simulation and use the switches to create all four possible pairs of input values. Observe the out value in each case and enter the results in the table below. Include a screenshot showing the states of the two inputs and the output. Verify that you get the truth table for the AND gate: Switch A Open A=0, Switch B Open B=0, F=0 Switch A Closed A=1, Switch B Open B=0, F=0 4
Switch A Open A=0, Switch B Closed B=1, F=0 Switch A Closed A=1, Switch B Closed B=1, F=1 A B F 0 0 0 0 1 0 1 0 0 1 1 1 5
Repeat the same exercise of building and testing the truth tables for OR, NAND, NOR, and XOR gates. Show the truth table and include one screenshot, as specified above, for each gate. OR A B F 0 0 0 0 1 1 1 0 1 1 1 1 6
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NAND A B F 0 0 1 0 1 1 1 0 1 1 1 0 NOR 7
A B F 0 0 1 0 1 0 1 0 0 1 1 0 XOR A B F 0 0 0 0 1 1 1 0 1 1 1 0 Finally, provide answers to the following questions: 1. What is the relationship between the AND gate and the NAND gate? An AND gate produces a high output (1) only when both of its inputs are high (1). A NAND gate, on the other hand, produces the opposite output. It outputs a low (0) only when both inputs are high; otherwise, it produces a high output. In essence, a NAND gate is the complement of an AND gate. If you connect an inverter (NOT gate) at the output of an AND gate, you essentially get a NAND gate. 2. What would happen if two inverters were connected in series? Connecting two inverters (NOT gates) in series results in a buffering effect. The logical operation of the combination is the same as having no inverters at all. If you have two inverters (A and B) in series: Input -> A -> B -> Output, the overall effect is equivalent to having a single inverter. The output will be the logical complement of the input. 8
3. Which gate outputs a zero only when both inputs are high? The gate that outputs a zero only when both inputs are high is the NAND gate. The NAND gate produces a low output (0) when both of its inputs are high (1), and it produces a high output for all other input combinations. 4. Which gate outputs a zero when both inputs are at the same logic level? The gate that outputs a zero when both inputs are at the same logic level is the XOR gate (exclusive OR). The XOR gate produces a low output (0) when both inputs are at the same logic level (either both high or both low), and it produces a high output for different input levels. Conclusion: This lab utilized digital AND, NAND, NOR, XOR, and OR gates, connected to switches and probes, to visually represent the various gates’ functions. Utilizing the visual cues of a lit or unlit probe, truth tables were constructed for when A, B, and F were 0. This lab was helpful in giving a visual representation to the various gates to show real time changes in the circuitry. 9
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