EXPERIMENT_2

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Feb 20, 2024

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EXPERIMENT#2 Inverting Logic: NOT, NAND, & NOR OBJECTIVES:  Examine inverting logic circuits.  Demonstrate the characteristics of NOT, NAND, and NOR gates.  Develop truth tables for NOT, NAND, and NOR gates. DISCUSSION: The inverter (or NOT gate) represents logical complementation. A NOT gate can have only one input and one output. The output of a NOT gate simply reverses (inverts) the logic value presented at its input. The NOT gate can be combined with AND and OR gates to construct two more basic gates: NAND and NOR gates. Both NAND and NOR gates are universal logic gates, which means that either NAND gates or NOR gates can be used to construct any combinational logic circuit. We will use gate symbols, truth tables, and Boolean equations to demonstrate their characteristics. As with AND and OR gates, NAND and NOR gates can have two or more inputs but only one output. Gate Characteristics: 1. The NOT Gate Symbol Boolean Equation Truth Table P a g e 1 | 10

Because the NOT gate has only one input, the truth table has two rows. Moreover, the output inverts the logic level of the input. In addition to the overhead bar shown above (read as “X = A- bar’), notation for logical inversion includes the following: 2. The NAND Gate Symbol Boolean Equation Truth Table The behavior of a NAND gate can be summarized as follows: The output is LOW only when all the inputs are HIGH . If one or more inputs are LOW (false or logic 0), the output will be HIGH. Comparing the truth table for the NAND gate with that of the AND gate, you will find out that each output of a NAND gate is exactly the opposite (inverted) logic value of the corresponding output of an AND gate . In fact, a NAND gate is functionally equivalent to an AND gate cascaded with a NOT gate as shown below. 3. The NOR Gate Symbol Boolean Equation Truth Table As seen from the truth table, the output of a NOR gate is HIGH only when all the inputs are LOW . If one or more of the inputs are HIGH, then the output is LOW. Similarly, a NOR gate can be constructed using an OR gate cascaded with a NOT gate. In other words, a NOR gate is functionally equivalent to an OR gate followed by an inverter. P a g e 2 | 10

NAND and NOR gates can be used to perform some useful functions such as enabling and disabling signals. Also, NAND and NOR gates can be used to perform the function of a NOT gate. PROCEDURE: Part I 1.) Implement 3-input NAND gate, 3-input NOR gate and NOT gate using VHDL. 2.) Define the input and output ports as following: P a g e 3 | 10

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3.) Type the gate-equivalent VHDL code for the NAND, NOR & NOT gates between the “begin” and “end Behavioral” . 4.) Use the xdc template from: https://www.xilinx.com/support/documentation/university/Vivado- Teaching/HDL-Design/2015x/Basys3/Supporting%20Material/Basys3_Master.xdc Copy and paste the whole text into your constraints file. Uncomment by deleting the # signs in front of the lines of switches and LEDs that we’re going to use. Modify the port names to match with port names defined in the design source as follows: P a g e 4 | 10

5.) Run synthesis, run implementation, and generate bitstream . If running synthesis or implementation failed, double check your design file (.vhd). If bitstream generation failed, double check your constraints file (.xdc) 6.) Program the target board. 7.) Toggle the switches, observe and verify your results 8.) Fill out the truth tables, draw schematic diagrams and write the Boolean equations. 9.) Answer post-experiment questions. RESULTS: Part I 1.) 3-input NAND Gate A2 A1 A0 X Schematic Diagram 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 Boolean Equation 1 1 0 1 X = A2 * A1 * A0 1 1 1 0 P a g e 5 | 10

2.) 3-input NOR Gate B2 B1 B0 Y Schematic Diagram 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 Boolean Equation 1 1 0 0 Y = B2 + B1 + B0 1 1 1 0 3.) NOT Gate C Z0 Schematic Diagram Boolean Equation 0 1 Z0 = C 1 0 Questions: 1.) Comment on your results. Do they agree with the statements in our Discussion section? They do, as a NOT gate can only have one input and one output and inverts the logic value supplied at its input. Additionally, both NAND and NOR gates are universal logic gates, meaning that anyone can be used to build any combinational logic circuit. 2.) Attach 2 photos of your BASYS 3 board results showing the following input conditions:  C = HIGH, B2 = LOW, B1 = LOW, B0 = LOW; A2 = HIGH, A1 = HIGH, A0 = HIGH P a g e 6 | 10

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 C = LOW, B2 = HIGH, B1 = HIGH, B0 = HIGH; A2 = LOW, A1 = LOW, A0 = LOW PROCEDURE: Part II 1.) Modify the previous .vhd source code in order to add the implementations of these gates. P a g e 7 | 10

2.) Modify the port names in the constraints file to match with updated port names defined in the design source as follows: (Nothing has changed for the switches section) P a g e 8 | 10

3.) Since the design has changed, you have to run synthesis, run implementation, and generate bitstream again. If running synthesis or implementation failed, double check your design file (.vhd). If bitstream generation failed, double check your constraints file (.xdc) 4.) Reprogram the target board with the updated .bit file. 5.) Toggle the switches, observe and verify your results 6.) Fill out the truth tables, draw schematic diagrams and write the Boolean equations. 7.) Answer post-experiment questions. RESULTS: Part II Z0 <= NOT C; Z1 <= C NAND C; Z2 <= C NOR '0'; C Z0 Z1 Z2 0 1 1 1 1 0 0 0 3.) What did you observe from the truth table above? What can we conclude about the use of NAND gate or NOR gate to construct a NOT gate? From the truth table , we notice that the outputs are HIGH when the input is LOW , and LOW when the input is HIGH . This truth table acts as the reverse of the input. Therefore, we can conclude that by using a NAND gate or a NOR gate, we can construct a NOT gate because both of these gates exhibit the same behavior as a NOT gate. P a g e 9 | 10

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4.) Attach 2 photos of your BASYS 3 board results showing the following input conditions:  C = LOW, B2 = LOW, B1 = LOW, B0 = LOW; A2 = LOW, A1 = LOW, A0 = LOW  C = HIGH, B2 = LOW, B1 = LOW, B0 = LOW; A2 = LOW, A1 = LOW, A0 = LOW (The photos should reflect the results of the updated design with Z1 and Z2.) P a g e 10 | 10