hw3 eecs112 2023

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Dec 6, 2023

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EECS 112: Computer Organization and Design Homework 3 – Single-cycle Processor, and Pipelining Due date: Tue Nov. 2 8 th, 2023, by 11:59 PM Problem 1 ( 20 points): Assume the following sequence of instructions is executed on a five-stage pipelined datapath: add x5, x10, x5 ld x28, 0(x5) ld x29,8(x5) add x29, x28, x29 add x6, x10, x11 Assume that the register write is done in the first half of a cycle and register read happens in the second half of a cycle. Draw multiple-clock-cycle pipeline diagrams for the following cases and answer questions : a) If there is no forwarding or hazard detection, insert NOPs to ensure correct execution. ( 7 points) b) Schedule the code to avoid as many NOPs as possible if there is no forwarding or hazard detection. What is the code sequence after scheduling? How many NOPs are avoided? ( 7 points) c) If forwarding is applied, schedule the code to avoid as many NOPs as possible and show forwarding path using connections between stages. ( 6 points) Hint : An example of a multiple-clock-cycle pipeline diagram (CC means clock cycle ): CC1 CC2 CC3 CC4 CC5 CC6 CC7 [Instruction 1] IF ID EX MEM WB NOP [Instruction 2] IF ID EX MEM WB The blue arrow represents a forwarding path from MEM to EX.

Problem 2 (5 points): When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get “broken” and always register a logical 0. This is often called a “stuck-at-0” fault. a) Which type(s) of instructions fail to operate correctly if the MemWrite wire is stuck at 0? (2 points) b) Which type(s) of instructions fail to operate correctly if the ALUSrc wire is stuck at 0? (3 points)

Problem 3 (5 points): Consider the following instruction mix: R-type I-type (non-ld) Load Store Branch Jump total 27% 24% 24% 15% 5% 5% 100% a) What fraction of all instructions uses data memory? (2 points) b) What fraction of all instructions uses instruction memory? (1 point) c) What fraction of all instructions uses the sign extend? (2 points) Problem 4 (5 points): Consider the following assembly code. Assume that x11 is initialized to 11 and x12 is initialized to 22. a) If running the code on a single-cycle processor, what would the final values of register x15 be? (2 points) b) Suppose you executed the code below on a version of the pipelined datapath that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). (3 points) Note: Assume the register file is written at the beginning of the cycle and read at the end of the cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. addi x11 , x12 , 5 add x13 , x11 , x12 addi x14 , x11 , 15 add x15 , x11 , x11

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Problem 5 (20 points): Assume that we have a simple processor which is able to execute 7 instructions: load doubleword (ld), store double world (sd), add (add), subtract (sub), AND (and), OR (or), and branch if equal (beq). Assume the operation times for the major functional units are in the table (assuming target address for beq instructions is calculated by ALU): Inst. Fetch Reg. Read ALU Operation Data Mem. Reg. Write 200ps 150ps 200ps 300ps 150ps a) If the processor is in single-cycle model, what are total times for load doubleword (ld), store doubleword (sd), R-format (add, sub, and, or), and branch if equal (beq) instructions, respectively (not counting the idle time within a clock period)? What is the (minimum) clock period? (10 points) b) If the processor is 5-stage pipelined (with steps Inst. Fetch, Reg. Read, ALU Operation, Data Mem., and Reg. Write), what is the (minimum) clock period? What is the execution time for a load doubleword (ld) instruction? (5 points) c) Suppose the following instructions run on the processor. ld x1,0(sp) ld x10,8(sp) add x7,x5,x6 What is the execution time if the processor is in single-cycle model? What is the execution time of the instructions in b) on the pipelined processor? What is the speedup comparing to the single-cycle processor? (5 points) (Hint: ࠵?࠵?࠵?࠵?࠵?࠵?࠵?࠵?࠵?_࠵?࠵?࠵?࠵? = ࠵?࠵?࠵?࠵?࠵?_࠵?࠵?࠵?࠵?࠵?_࠵?࠵?࠵?࠵?࠵?࠵? × ࠵?࠵?࠵?࠵?࠵?_࠵?࠵?࠵?࠵?࠵?࠵? .)

Problem 6 (5 points): Assume that the following RISC-V code is executed on a pipelined processor with a 5-stage pipeline with full forwarding and a “always-taken” branch predictor. Draw the pipeline diagram and report number of clock cycles it takes to execute this sequence of instructions. LABEL1: lw x5, 0(x10) beq x6, x11, LABEL2 # Taken add x6, x6, x5 LABEL2: beq x7, x12, LABEL1 # Not Taken and x7, x7, x5 Note : Result of branch is determined in EX stage. Comments denote the true situation.

Problem 7 (1 5 points): Find and compare the percentage of accuracy for 1-bit branch predictor and 2-bit branch predictor for the following loop: addi x10, x0, 3 addi x11, x0, 3 LOOP: addi x10, x10, -1 bne x10, x0, LOOP addi x11, x11, -1 addi x10, x0, 3 bne x11, x0, LOOP nop Complete the table below for each method. Start from “taken” state for the 1-bit predictor. Start from “strong taken” state for the 2-bit predictor. Assume all branch instructions share the same predictor in a program. 1-bit predictor state transition diagram 2-bit predictor state transition diagram

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1-bit predictor 2-bit predictor prediction outcome prediction outcome X10 = 2 X11 = 3 X10 = 2 X11 = 3 X10 = 1 X11 = 3 X10 = 1 X11 = 3 X10 = 0 X11 = 3 X10 = 0 X11 = 3 X10 = 3 X11 = 2 X10 = 3 X11 = 2 X10 = 2 X11 = 2 X10 = 2 X11 = 2 X10 = 1 X11 = 2 X10 = 1 X11 = 2 X10 = 0 X11 = 2 X10 = 0 X11 = 2 X10 = 3 X11 = 1 X10 = 3 X11 = 1 X10 = 2 X11 = 1 X10 = 2 X11 = 1 X10 = 1 X11 = 1 X10 = 1 X11 = 1 X10 = 0 X11 = 1 X10 = 0 X11 = 1 X10 = 3 X11 = 0 X10 = 3 X11 = 0 Accuracy percentage = Accuracy percentage =

Problem 8 (1 5 points): Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC- V. Interpretation: Mem[Reg[rs1]] = Reg[rs2]+imm . To implement this, we only need to add more MUXs in EX stage. a) How many more MUXs do we need to add ? (4 points) b) What new signals do we need (if any) from the control unit to support this instruction? (1 point) c) Add the MUXs and necessary wires in the second figure below to demonstrate an implementation of this new instruction. (Just draw the added part.) (10 points)

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