ICS 232 Homework 7: Key Concepts in Computer Architecture

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 Name: Key Note: Please post your homework to ICS232 D2L on or before the due date. Irvine Chapter 4 – Data Transfers, Addressing, Arithmetic 1. In a MOV instruction, which operand is the source and which is the destination? Operand 1 is the destination and operand 2 is the source. For example MOV EAX, 10 moves 10 into EAX 2. (True/False): The EIP register cannot be the destination operand of a MOV instruction. True 3. In the operand notation used by Intel, what does reg/mem32 indicate? The operand may be either a 32-bit register or a 32-bit memory location. 4. What will be the value of the destination operand after each of these instructions? var2 WORD 1000h, 2000h, 3000h, 4000h var3 SWORD -16, -42 var4 DWORD 12345 MOV AX, var2 a. 1000h MOV AX, [var2 + 4] b. 3000h MOV AX, var3 c. FFF0h MOV AX, [var3 - 2] d. 4000h MOV AX, LENGTHOF var2 e. 0004h MOV AX, SIZEOF var3 f. 0004h 5. Write instructions that subtract val4 from val2.

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 MOV EAX, val4 SUB val2, EAX MOV EAX, val2 SUB EAX, val4 MOV val2, EAX 6. What will be in the registers as executing this code myBytes BYTE 10h,20h,30h,40h myWords WORD 8Ah,3Bh,72h,44h,66h myDoubles DWORD 1,2,3,4,5 myPointer DWORD myDoubles mov esi,OFFSET myBytes mov al,[esi] ; a. AL = 10h mov al,[esi+3] ; b. AL = 40h mov esi,OFFSET myWords + 2 mov ax,[esi] ; c. AX = 003Bh mov edi,8 mov edx,[myDoubles + edi] ; d. EDX = 3 mov edx,myDoubles[edi] ; e. EDX = 3 mov ebx,myPointer mov eax,[ebx+4] ; f. EAX = 2 7. What will be the final value of EAX in this example? mov eax,0 mov ecx,10 ; outer loop counter L1: mov eax,3 mov ecx,5 ; inner loop counter L2: add eax,5 loop L2 ; repeat inner loop loop L1 ; repeat outer loop

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 Answer: This is a trick! The program does not stop, because the first LOOP instruction decrements ECX to zero. The second LOOP instruction decrements ECX to FFFFFFFFh, causing the outer loop to repeat. Prepare for next class by reading lecture notes Irvine Chapter 5 and 6 Complete Project 1 Continue working on Your Group Project Optional Questions: 1. Now that the semester is about one-half way complete, do you have any comments about the first half and how would you like the second half to be improved? Name: Key Note: Please post your homework to ICS232 D2L on or before the due date. 1. Show the value of AL for the instructions below: mov al,7Ah not al a. 85h mov al,3Dh and al,74h b. 34h mov al,9Bh or al,35h c. BFh mov al,72h xor al,0DCh d. AEh 2. Will the following code jump to the label named target? mov ax,8109h cmp ax,26h jg target

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 a. No (8109h is negative, and 26h is positive) mov ax,8109h cmp ax,26h ja target b. Yes (unsigned compare) mov eax,8109h cmp eax,26h jg target c. Yes (32-bit comparison) mov bx,8109h movsx eax,bx cmp eax,26h jg target d. No (8109h is negative, and 26h is positive) 3. Write instructions that jump to label L1 when the unsigned integer in DX is less than or equal to the integer in CX. cmp dx,cx jbe L1 4. Write instructions that jump to label L2 when the signed integer in AX is greater than the integer in CX. cmp ax,cx jg L2 5. Using the LOOP write the code to sum the positive entries in an array of SWORDs.

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 .data array SWORD -3,-6,-1,-10,10,30,40,4 .code mov esi,OFFSET array mov ecx,LENGTHOF array xor ax,ax ; initialize sum L1: mov bx,WORD PTR [esi] ; load next entry test bx,bx ; test sign bit js L2 ; jump if negative add ax,bx ; compute sum L2: add esi,TYPE array ; move to next position loop L1 ; continue loop quit: 6. Implement the following pseudocode in assembly language assuming signed numbers: if (edx <= ecx) x = 1; else x = 2; cmp edx,ecx jg L1 mov X,1 jmp next L1: mov X,2 next: 7. Implement the following pseudocode in assembly language assuming unsigned numbers: if ((val1 > ecx) && (ecx > edx))

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 x = 1; else x = 2; cmp val1,ecx jna L1 cmp ecx,edx jna L1 mov x,1 jmp next L1: mov x,2 next: Prepare for next class by reading lecture notes Irvine Chapter 7 and 8 Continue working on Project 2 Continue working on Your Group Project Name: Key Note: Please post your homework to ICS232 D2L on or before the due date. 1. Which instruction shifts each bit in an operand to the left and copies the highest bit into both the Carry flag and the lowest bit position? ROL 2. Which instruction shifts each bit to the right, copies the lowest bit into the Carry flag, and copies the Carry flag into the highest bit position? RCR 3. What is the value of AL after each instruction?

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 MOV AL, 0D4h SHR AL, 1 a. 6Ah MOV AL, 0D4h SAR AL, 1 b. EAh MOV AL, 0D4h SAR AL, 4 c. FDh MOV AL, 0D4h ROL AL, 1 d. A9h 4. Write the assembly language instructions to multiple EAX by 24 using shift instructions. MOV EBX, EAX SHL EAX, 4 ; multiply by 16 SHL EBX, 3 ; multiply by 8 ADD EAX, EBX 5. Explain why overflow cannot occur when the MUL and one-operand IMUL instructions execute. The product is stored in registers that are twice the size of the multiplier and multiplicand. If you multiply 0FFh by 0FFh, for example, the product (FE01h) easily fits within 16 bits. 6. When EBX is the operand in a DIV instruction, which register holds the quotient? EAX 7. When BX is the operand in a DIV instruction, which register holds the quotient? AX 8. What will be the contents of AX and DX after the following operation?

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 mov dx,0 mov ax,222h mov cx,100h mul cx DX = 0002, AX = 2200 9. What will be the contents of AX and DX after the following operation? mov ax,63h mov bl,10h div bl AL = 06, AH = 03 10. Implement the following C expression in assembly language, using 32-bit integer signed operands: val1 = (val2 / val3) * (val1 + val2); MOV EAX, val2 CDQ IDIV val3 ; val2 / val3 MOV EBX, EAX ; save result MOV EAX, val1 ADD EAX, val2 ; val1 + val2 IMUL EAX, EBX ; multiply MOV val1, EAX ; save result val1 SDWORD 0 val2 SDWORD 0 val3 SDWORD 0 11. Implement the following C code fragment in assembly language, using 32-bit integer signed operands:

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 int test(int x, int y) { int r; if (x > y) r = x * y; else if (x == y) r = x / y; else r = x + y; return (r); } test proc push ebp mov ebp, esp sub esp, 4 mov eax, DWORD PTR 8[ebp] ; x cmp eax, DWORD PTR 12[ebp] ; y jle elseif imul eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax ; r jmp endif elseif: jne else cdq idiv DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax jmp endif else: add eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax endif: mov eax, DWORD PTR -4[ebp] mov esp, ebp pop ebp ret test endp

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 64-bit: push rbp mov rbp, rsp mov Dword ptr[rbp-20], edi ; save x mov Dword ptr[rbp-24], esi ; save y mov eax, Dword ptr[rbp-20] cmp eax, Dword ptr [rbp-24] jle L2 mov eax, Dword ptr[rbp-20] imul eax, Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax ; save r jmp L3 L2: mov eax, Dword ptr[rbp-20] cmp eax, WDword ptr[rbp-24] jne L4 mov eax, Dword ptr[rbp-20] cdq idiv Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax jmp L3 L4: mov edx, Dword ptr[rbp-20] mov eax, Dword ptr[rbp-24] add eax, edx mov Dword ptr[rbp-4], eax L3: mov eax, Dword ptr[rbp-4] pop rbp ret 12. What is the equivalent C code? whatDoIDo proc 0000 55 push ebp 0001 89E5 mov ebp, esp

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 000d 8B4508 mov eax, DWORD PTR 8[ebp] 0010 99 cdq 0011 F77D0C idiv DWORD PTR 12[ebp] 0014 89D0 mov eax, edx 0016 5D pop ebp 0017 C3 ret whatDoIDo endp int whatDoIDo(int x, int y) { return (x % y); } Prepare for next class by reading Chapter 6 – Memory Start working on Project 2 Continue working on Your Group Project Name: Key Note: Please post your homework to ICS232 D2L on or before the due date. 1. Which instruction shifts each bit in an operand to the left and copies the highest bit into both the Carry flag and the lowest bit position? ROL 2. Which instruction shifts each bit to the right, copies the lowest bit into the Carry flag, and copies the Carry flag into the highest bit position? RCR 3. What is the value of AL after each instruction?

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 MOV AL, 0D4h SHR AL, 1 a. 6Ah MOV AL, 0D4h SAR AL, 1 b. EAh MOV AL, 0D4h SAR AL, 4 c. FDh MOV AL, 0D4h ROL AL, 1 d. A9h 4. Write the assembly language instructions to multiple EAX by 24 using shift instructions. MOV EBX, EAX SHL EAX, 4 ; multiply by 16 SHL EBX, 3 ; multiply by 8 ADD EAX, EBX 5. Explain why overflow cannot occur when the MUL and one-operand IMUL instructions execute. The product is stored in registers that are twice the size of the multiplier and multiplicand. If you multiply 0FFh by 0FFh, for example, the product (FE01h) easily fits within 16 bits. 6. When EBX is the operand in a DIV instruction, which register holds the quotient? EAX 7. When BX is the operand in a DIV instruction, which register holds the quotient? AX 8. What will be the contents of AX and DX after the following operation? mov dx,0

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 mov ax,222h mov cx,100h mul cx DX = 0002, AX = 2200 9. What will be the contents of AX and DX after the following operation? mov ax,63h mov bl,10h div bl AL = 06, AH = 03 10. Implement the following C expression in assembly language, using 32-bit integer signed operands: val1 = (val2 / val3) * (val1 + val2); MOV EAX, val2 CDQ IDIV val3 ; val2 / val3 MOV EBX, EAX ; save result MOV EAX, val1 ADD EAX, val2 ; val1 + val2 IMUL EAX, EBX ; multiply MOV val1, EAX ; save result val1 SDWORD 0 val2 SDWORD 0 val3 SDWORD 0 11. Implement the following C code fragment in assembly language, using 32-bit integer signed operands: int test(int x, int y)

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 { int r; if (x > y) r = x * y; else if (x == y) r = x / y; else r = x + y; return (r); } test proc push ebp mov ebp, esp sub esp, 4 mov eax, DWORD PTR 8[ebp] ; x cmp eax, DWORD PTR 12[ebp] ; y jle elseif imul eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax ; r jmp endif elseif: jne else cdq idiv DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax jmp endif else: add eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax endif: mov eax, DWORD PTR -4[ebp] mov esp, ebp pop ebp ret test endp

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 64-bit: push rbp mov rbp, rsp mov Dword ptr[rbp-20], edi ; save x mov Dword ptr[rbp-24], esi ; save y mov eax, Dword ptr[rbp-20] cmp eax, Dword ptr [rbp-24] jle L2 mov eax, Dword ptr[rbp-20] imul eax, Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax ; save r jmp L3 L2: mov eax, Dword ptr[rbp-20] cmp eax, WDword ptr[rbp-24] jne L4 mov eax, Dword ptr[rbp-20] cdq idiv Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax jmp L3 L4: mov edx, Dword ptr[rbp-20] mov eax, Dword ptr[rbp-24] add eax, edx mov Dword ptr[rbp-4], eax L3: mov eax, Dword ptr[rbp-4] pop rbp ret 12. What is the equivalent C code? whatDoIDo proc 0000 55 push ebp 0001 89E5 mov ebp, esp 000d 8B4508 mov eax, DWORD PTR 8[ebp]

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 0010 99 cdq 0011 F77D0C idiv DWORD PTR 12[ebp] 0014 89D0 mov eax, edx 0016 5D pop ebp 0017 C3 ret whatDoIDo endp int whatDoIDo(int x, int y) { return (x % y); } Prepare for next class by reading Chapter 6 – Memory Start working on Project 2 Continue working on Your Group Project Name: Key Note: Please post your homework to ICS232 D2L on or before the due date. 1. Which instruction shifts each bit in an operand to the left and copies the highest bit into both the Carry flag and the lowest bit position? ROL 2. Which instruction shifts each bit to the right, copies the lowest bit into the Carry flag, and copies the Carry flag into the highest bit position? RCR 3. What is the value of AL after each instruction? MOV AL, 0D4h SHR AL, 1 a. 6Ah

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 MOV AL, 0D4h SAR AL, 1 b. EAh MOV AL, 0D4h SAR AL, 4 c. FDh MOV AL, 0D4h ROL AL, 1 d. A9h 4. Write the assembly language instructions to multiple EAX by 24 using shift instructions. MOV EBX, EAX SHL EAX, 4 ; multiply by 16 SHL EBX, 3 ; multiply by 8 ADD EAX, EBX 5. Explain why overflow cannot occur when the MUL and one-operand IMUL instructions execute. The product is stored in registers that are twice the size of the multiplier and multiplicand. If you multiply 0FFh by 0FFh, for example, the product (FE01h) easily fits within 16 bits. 6. When EBX is the operand in a DIV instruction, which register holds the quotient? EAX 7. When BX is the operand in a DIV instruction, which register holds the quotient? AX 8. What will be the contents of AX and DX after the following operation? mov dx,0 mov ax,222h mov cx,100h

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 mul cx DX = 0002, AX = 2200 9. What will be the contents of AX and DX after the following operation? mov ax,63h mov bl,10h div bl AL = 06, AH = 03 10. Implement the following C expression in assembly language, using 32-bit integer signed operands: val1 = (val2 / val3) * (val1 + val2); MOV EAX, val2 CDQ IDIV val3 ; val2 / val3 MOV EBX, EAX ; save result MOV EAX, val1 ADD EAX, val2 ; val1 + val2 IMUL EAX, EBX ; multiply MOV val1, EAX ; save result val1 SDWORD 0 val2 SDWORD 0 val3 SDWORD 0 11. Implement the following C code fragment in assembly language, using 32-bit integer signed operands: int test(int x, int y) { int r;

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 if (x > y) r = x * y; else if (x == y) r = x / y; else r = x + y; return (r); } test proc push ebp mov ebp, esp sub esp, 4 mov eax, DWORD PTR 8[ebp] ; x cmp eax, DWORD PTR 12[ebp] ; y jle elseif imul eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax ; r jmp endif elseif: jne else cdq idiv DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax jmp endif else: add eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax endif: mov eax, DWORD PTR -4[ebp] mov esp, ebp pop ebp ret test endp 64-bit:

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 push rbp mov rbp, rsp mov Dword ptr[rbp-20], edi ; save x mov Dword ptr[rbp-24], esi ; save y mov eax, Dword ptr[rbp-20] cmp eax, Dword ptr [rbp-24] jle L2 mov eax, Dword ptr[rbp-20] imul eax, Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax ; save r jmp L3 L2: mov eax, Dword ptr[rbp-20] cmp eax, WDword ptr[rbp-24] jne L4 mov eax, Dword ptr[rbp-20] cdq idiv Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax jmp L3 L4: mov edx, Dword ptr[rbp-20] mov eax, Dword ptr[rbp-24] add eax, edx mov Dword ptr[rbp-4], eax L3: mov eax, Dword ptr[rbp-4] pop rbp ret 12. What is the equivalent C code? whatDoIDo proc 0000 55 push ebp 0001 89E5 mov ebp, esp 000d 8B4508 mov eax, DWORD PTR 8[ebp] 0010 99 cdq 0011 F77D0C idiv DWORD PTR 12[ebp]

ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 0014 89D0 mov eax, edx 0016 5D pop ebp 0017 C3 ret whatDoIDo endp int whatDoIDo(int x, int y) { return (x % y); } Prepare for next class by reading Chapter 6 – Memory Start working on Project 2 Continue working on Your Group Project Name: Key Note: Please post your homework to ICS232 D2L on or before the due date. 1. Which instruction shifts each bit in an operand to the left and copies the highest bit into both the Carry flag and the lowest bit position? ROL 2. Which instruction shifts each bit to the right, copies the lowest bit into the Carry flag, and copies the Carry flag into the highest bit position? RCR 3. What is the value of AL after each instruction? MOV AL, 0D4h SHR AL, 1 a. 6Ah MOV AL, 0D4h

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 SAR AL, 1 b. EAh MOV AL, 0D4h SAR AL, 4 c. FDh MOV AL, 0D4h ROL AL, 1 d. A9h 4. Write the assembly language instructions to multiple EAX by 24 using shift instructions. MOV EBX, EAX SHL EAX, 4 ; multiply by 16 SHL EBX, 3 ; multiply by 8 ADD EAX, EBX 5. Explain why overflow cannot occur when the MUL and one-operand IMUL instructions execute. The product is stored in registers that are twice the size of the multiplier and multiplicand. If you multiply 0FFh by 0FFh, for example, the product (FE01h) easily fits within 16 bits. 6. When EBX is the operand in a DIV instruction, which register holds the quotient? EAX 7. When BX is the operand in a DIV instruction, which register holds the quotient? AX 8. What will be the contents of AX and DX after the following operation? mov dx,0 mov ax,222h mov cx,100h mul cx

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 DX = 0002, AX = 2200 9. What will be the contents of AX and DX after the following operation? mov ax,63h mov bl,10h div bl AL = 06, AH = 03 10. Implement the following C expression in assembly language, using 32-bit integer signed operands: val1 = (val2 / val3) * (val1 + val2); MOV EAX, val2 CDQ IDIV val3 ; val2 / val3 MOV EBX, EAX ; save result MOV EAX, val1 ADD EAX, val2 ; val1 + val2 IMUL EAX, EBX ; multiply MOV val1, EAX ; save result val1 SDWORD 0 val2 SDWORD 0 val3 SDWORD 0 11. Implement the following C code fragment in assembly language, using 32-bit integer signed operands: int test(int x, int y) { int r;

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 if (x > y) r = x * y; else if (x == y) r = x / y; else r = x + y; return (r); } test proc push ebp mov ebp, esp sub esp, 4 mov eax, DWORD PTR 8[ebp] ; x cmp eax, DWORD PTR 12[ebp] ; y jle elseif imul eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax ; r jmp endif elseif: jne else cdq idiv DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax jmp endif else: add eax, DWORD PTR 12[ebp] mov DWORD PTR -4[ebp], eax endif: mov eax, DWORD PTR -4[ebp] mov esp, ebp pop ebp ret test endp 64-bit: push rbp

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 mov rbp, rsp mov Dword ptr[rbp-20], edi ; save x mov Dword ptr[rbp-24], esi ; save y mov eax, Dword ptr[rbp-20] cmp eax, Dword ptr [rbp-24] jle L2 mov eax, Dword ptr[rbp-20] imul eax, Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax ; save r jmp L3 L2: mov eax, Dword ptr[rbp-20] cmp eax, WDword ptr[rbp-24] jne L4 mov eax, Dword ptr[rbp-20] cdq idiv Dword ptr[rbp-24] mov Dword ptr[rbp-4], eax jmp L3 L4: mov edx, Dword ptr[rbp-20] mov eax, Dword ptr[rbp-24] add eax, edx mov Dword ptr[rbp-4], eax L3: mov eax, Dword ptr[rbp-4] pop rbp ret 12. What is the equivalent C code? whatDoIDo proc 0000 55 push ebp 0001 89E5 mov ebp, esp 000d 8B4508 mov eax, DWORD PTR 8[ebp] 0010 99 cdq 0011 F77D0C idiv DWORD PTR 12[ebp] 0014 89D0 mov eax, edx

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 0016 5D pop ebp 0017 C3 ret whatDoIDo endp int whatDoIDo(int x, int y) { return (x % y); } Prepare for next class by reading Chapter 6 – Memory Start working on Project 2 Continue working on Your Group Project Name: Key Note: Please post your homework to ICS232 D2L on or before the due date. Chapter 9 – Alternative Architectures Essential Terms and Concepts 3. Describe how register windowing makes procedure call more efficient? Storing parameters in registers is much faster than storing them in the stack. Therefore, the speed of procedures call can be improved. 7. Do all programming problems lend themselves to parallel execution? What is the limiting factor? No. Many times serial execution is required to merge data from parallel tasks. 12. Explain the limitation inherent in a register-register vector processing machine?

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 The number of registers limits the number of elements that can be processed at one time. 13. Give two reasons for the efficiency of vector processors. Fewer instructions are executed and there is a continuous source of data so pre-fetching can occur. 21. What is reentrant code? The same code can be executed at the same time by multiple threads. Exercises 1. Why do RISC machines operate on registers? RISC machines limit the instructions that can access memory to load and store instructions only. This means that all other instructions use registers. This requires fewer cycles and speeds up the execution of the code and, thus, the performance of the hardware. The goal for RISC architectures is to achieve single-cycle instructions, which would not be possible if instructions had to access memory instead of registers. 4. Suppose a RISC machine uses overlapping register windows with: • 10 global registers • 6 input parameter registers • 10 local registers • 6 output parameter registers How large is each overlapping register window? 6 6. A RISC processor has 152 total registers, with 12 designated as global registers. The 10 register windows each have 6 input registers and 6 output registers. How many local

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 registers are in each register window set? HINT: Remember, due to the circular nature of the windows, the output registers of the last window are shared as the input registers of the first window. 152 = 12 + 10 x (local + 6) local = 8 9. Recall our discussions from Chapter 8 regarding context switches. These occur when one process stops using the CPU and another process begins. In this sense, register windows could be viewed as a potential weakness of RISC. Explain why this is the case. During a context switch, all information about the currently executing process must be saved, including the values in the register windows. When the process is restored, the values in the register windows must be restored as well. Depending on the size of the windows, this could be a very time-consuming process. 13. Explain the difference between loosely coupled and tightly coupled architectures. Loosely coupled and tightly coupled are terms that describe how multiprocessors deal with memory. If there is one large, centralized, shared memory, we say the system is tightly coupled. If there are multiple, physically distributed memories, we say the system is loosely coupled. 21. Why are distributed systems desirable? Distributed systems allow for resource sharing (such as sharing of printers and files), and thus, can reduce system cost. They also allow for redundancy, which increases reliability (if one site fails, the remaining sites can still function). These systems also speed up computation, as jobs can be distributed and run concurrently at many sites. Lastly, distributed systems run programs that, due to the nature of the system, can share data with other systems more easily via the communications network and communicate with remote sites.

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ICS 232 Computer Organization & Architecture Homework 7 – Irvine Chapter 2 & 4 - 10 points Due Date: 6/30/2022 28. Compare and contrast supervised learning and unsupervised learning with regard to neural networks. Supervised learning assumes that for each input, the output is known a priori. In unsupervised learning, no outputs are known in advance. 33. Indicate whether each of the following applies to CISC or RISC by placing either a C (for CISC) or an R (for RISC) in the blank. __ R __ 1. Simple instructions averaging 1 clock cycle to execute __ C __ 2. Single register set __ R __ 3. Complexity is in the compiler __ R __ 4. Highly pipelined __ C __ 5. Any instruction can reference memory __ C __ 6. Instructions are interpreted by the microprogram __ R __ 7. Fixed length, easily decoded instruction format __ C __ 8. Highly specialized, infrequently used instructions __ R __ 9. Use of overlapping register windows __ R __ 10. Relatively few addressing modes Prepare for Final Exam Complete Project 2 Continue working on Your Group Project Continue working on Homework 14 (Bonus)

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Homework 7 - Answers

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