Lab 4 - Logic Gates

Page 1 of 7 Seneca College School of Software Design and Data Science - SDDS SEH300 – Digital and Analog Circuits Lab 4: Logic Gates Important Instructions: 1. This is a group work, but you need to finish this lab and submit your individual lab report on blackboard by the due date. 2. Read the lab document. Finish the Procedure part and prepare your lab report. Answer the questions by using bold blue fonts . Finish all steps, fill in the tables, and answer the questions on the lab report document. Submit the lab report ONLY. 3. Submissions by email will not be considered. Zero mark will be granted for submissions after due date. 4. Remember always, units are important to be provided with your results. 5. After finishing your lab, write your name on the document as follows: Your First Name. Your Last Name - Lab 4 . Drop your lab in the corresponding drop box. Introduction: Logic deals with only two normal conditions: logic “1” or logic “0.” These conditions are like the yes o r no answers to a question. Either a switch is closed (1) or it isn’t (0); eithe r an event has occurred (1) or it hasn’t (0); and so on. In Boolean logic, 1 and 0 represent conditions. In positive logic, 1 is represented by the term HIGH and 0 is represented by the term LOW. In positive logic, the more positive voltage is 1 and the less positive voltage is 0. Thus, for positive TTL logic, a voltage of +2.4 V = 1 and a voltage of +0.4 V = 0. In some systems, this definition is reversed. With negative logic, the more positive voltage is 0 and the less positive voltage is 1. Thus, for negative TTL logic, a voltage of +0.4 V = 1 and a voltage of +2.4 V = 0. Negative logic is sometimes used for emphasizing an active logic level. For all of the basic gates, there is a traditional symbol that is used for positive logic and an alternate symbol for negative logic. For example, an AND gate can be shown in negative logic with an OR symbol an d “inverting bubbles” on the input and output, as illustrated with the three symbols in Figure 4-1 (a) . This logic can be read as “If A or B is LOW, the output is LOW.” The exact same gate can be drawn as in Figure 4-1 (b) , where it is now shown as a traditional active-HIGH gate and read as “If both A and B are HIGH, the output is HIGH.” The different drawings merely emphasize one or the other of the following two rules for an AND gate: Rule 1: If A is LOW or B is LOW or both are LOW, then X is LOW. Rule 2: If A is HIGH and B is HIGH, then X is HIGH.

Page 2 of 7 Figure 4-1: Two distinctive shape symbols for an AND gate. The two symbols represent the same gate. The operation can also be shown by the truth table. The AND truth table is Notice that the first rule describes the first three lines of the truth table and the second rule describes the last line of the truth table. Although two rules are needed to specify completely the operation of the gate, each of the equivalent symbols best illustrates only one of the rules. If you are reading the symbol for a gate, read a bubble as a logic 0 and the absence of a bubble as a logic 1. The first three lines of the truth table are illustrated with the negative-logic OR symbol ( Figure 4-1 (a) ); the last line of the truth table is illustrated with the positive-logic AND symbol ( Figure 4-1 (b) ). Similar rules and logic diagrams can be written for the other basic gates. A useful method of dealing with negative logic is to label the signal function with a bar written over the label to indicate that the signal is LOW when the stated condition is true. Figure 4-2 shows some examples of this logic, called assertion-level logic. You should be aware that manufacturers are not always consistent in the way labels are applied to diagrams and function tables.

Page 4 of 7 Figure 4-3: Basic logic gates. The logical operation of any gate can be summarized with a truth table, which shows all the possible inputs and outputs. The truth tables for INVERT, AND, OR, XOR, and XNOR are shown in Table 4 - 1(a) through (e) . The tables are shown with 1 and 0 to represent positive logic HIGH and LOW, respectively. Except in Figure 4 - 1(a) (where negative logic is illustrated), only positive logic is used in this lab and 1 and 0 mean HIGH and LOW, respectively.

Page 5 of 7 In this experiment, you will test the truth tables for NAND and NOR gates as well as those for several combinations of these gates. Keep in mind that if any two truth tables are identical, then the logic circuits that they represent are equivalent. In the Further Investigation , look for this idea of equivalence between a 4-gate circuit and a simpler 1-gate equivalent. Objectives: The key objectives of this lab are: 1. Determine experimentally the truth tables for the NAND, NOR, and inverter gates. 2. Use NAND and NOR gates to formulate other basic logic gates. 3. Use the ANSI/IEEE Std. 91-1984 logic symbols.

Page 7 of 7 For Further Investigation The circuit shown in Figure 4-10 has the same truth table as one of the truth tables shown in Table 4-1(a) through (e) . Test all input combinations and complete truth Table 4-10 . What is the equivalent gate?