CSCE_3730_F23_HW5

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University of North Texas *

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2100

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Dec 6, 2023

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© 2023 Robin Pottathuparambil Page 1 of 1 Homework #5 CSCE 3730 - Reconfigurable Logic Fall 2023 100 Points Due: 11/13/2023, 11:55 PM Instructions: Clearly show all the steps and complete the homework either typed in word or handwritten. Do not copy and paste figures or text from the lecture notes. Please type all the software/HDL code(s) in the homework document. Convert the typed in document into a single PDF. In the case of handwritten document, scan it and convert it into PDF. Do not handwrite code. Do not create an archive (zip, tar, or rar) file for your submission. Not following the above instructions could result in up to 50% deduction from your homework score . Upload all the materials to Canvas on or before the due date and time. Late submissions are not allowed. 1. What is the difference (at least two) between a latch and a flip-flop? (4 Points) 2. What are the applications (at least two) of a latch and flip-flop? (4 Points) 3. What is the difference between level, positive edge, and negative edge triggered flip-flop? (3 Points) 4. What are the applications (at least two) of SR, D, JK, and T flip-flop? (8 Points) 5. What is a digital clock signal? Define clock period, clock cycle, and clock frequency. (4 Points) 6. What is an FSM (Finite State Machine)? What is the difference between Moore and Mealy FSMs (describe with block diagrams)? (8 Points) 7. List the steps involved in an FSM design process? (6 Points) 8. Draw the state diagram and derive the state table for a 4-bit counter that counts through the terms of a sequence where the terms are defined as a n = a n-1 + 2a n-2 - 1 with the initial terms as a 1 = 1 and a 2 = 2. Clearly mark the start/reset state. (13 Points) 9. Write a VHDL code that implements an FSM for a 4-bit counter that counts through the terms of the sequence where the terms are defined as a n = a n-1 + 2a n-2 - 1. The initial terms are input to the VHDL design and make sure an asynchronous active high reset is used to reset the FSM. Assume the initial terms are 4-bit non-zero positive values and a 1 < a 2 . Write a test bench to test the counter’s reset and test the counter with four sets of inputs. (20 Points) 10. Design a Moore FSM (only state diagram and state table) that can detect the sequence 0, 0, 1, 0, 1. Write a VHDL code that implements the FSM. Write a VHDL test bench to test the FSM using ten 1-bit test inputs. (30 Points)
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