Homework 4

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Montclair State University *

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Computer Science

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Feb 20, 2024

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CSIT 545 (Fall 2023) Homework #4 (Due November 8,2023 by 11:59 PM on Canvas “Assignment”) Please answer the following questions regarding Datapath and control. a. [ 45 Points ] Recall that in Homework 2 Question 1, we came up the following RISC-V code to implement the C code “ A[9]=B[7]-5” : Lw x9, 28(x23) // load B[7] to x9 addi x9 , x9, -5 // Calculate B[7] -5 and put the result in x9 sw x9 ,36(x22) // store the value of x9 to A[9] For each line of the RISC-V code, please specify the values of the 9 control signals (i.e., Branch, MemRead, MemReg, ALUop, MemWrite, ALUSrc, RegWrite, ALUControl, and PCSrc) when the code is executed in the non-pipelined Datapath above. Please explain why the control signals are set this way for each line of the code. Non-pipelined Datapath Control Signals for Each Line of RISC-V Code: Lw x9, 28(x23): Branch: 0 (no branching) MemRead: 1 (read from memory) MemReg: 1 (write to register file) ALUop: 0 (add)

MemWrite: 0 (no write to memory) ALUSrc: 1 (ALU source is immediate) RegWrite: 1 (write to register file) ALUControl: 0010 (add) PCSrc: 0 (PC + 4) addi x9, x9, -5: Branch: 0 (no branching) MemRead: 0 (no read from memory) MemReg: 0 (no write to register file) ALUop: 0 (add) MemWrite: 0 (no write to memory) ALUSrc: 1 (ALU source is immediate) RegWrite: 1 (write to register file) ALUControl: 0010 (add) PCSrc: 0 (PC + 4) sw x9, 36(x22): Branch: 0 (no branching) MemRead: 0 (no read from memory) MemReg: 0 (no write to register file) ALUop: 0 (add) MemWrite: 1 (write to memory) ALUSrc: 1 (ALU source is immediate) RegWrite: 0 (no write to register file)

ALUControl: 0010 (add) PCSrc: 0 (PC + 4) Explanation: The control signals are set this way to perform the specified operations for each instruction. The Lw instruction loads data from memory and writes it to a register, so MemRead and MemReg are set to 1 to enable reading from memory and writing to the register file. The ALU is used to calculate the effective memory address (ALUop is set to 0 for addition). ALUSrc is set to 1 to use the immediate value for the address calculation. For addi and sw, the control signals are set appropriately based on their specific operations. Non-pipelined Datapath Control Signals: For each line of the RISC-V code, we specified the control signals as follows: Lw x9, 28(x23): MemRead and MemReg are set to 1 because we need to read data from memory and write the result to the register file. ALUop is set to 0 (add) because we are calculating the effective memory address by adding an offset to the base address in x23. ALUSrc is set to 1 because the ALU source is the immediate value (28 in this case). RegWrite is set to 1 to enable writing the result to the register file. ALUControl is set to 0010, which corresponds to an add operation. PCSrc is set to 0 because the next instruction's address is PC + 4 (no branching). addi x9, x9, -5: ALUop is set to 0 (add) because this instruction performs an addition operation. ALUSrc is set to 1 because the source of the ALU operation is an immediate value (-5 in this case). RegWrite is set to 1 to enable writing the result to the register file. ALUControl is set to 0010, corresponding to an add operation. Other control signals are set to 0 since this instruction doesn't involve memory access or branching. PCSrc is set to 0 to continue fetching the next sequential instruction. sw x9, 36(x22):

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MemWrite is set to 1 because we are writing data to memory. ALUop is set to 0 (add) because we are calculating the effective memory address by adding an offset to the base address in x22. ALUSrc is set to 1 because the ALU source is the immediate value (36 in this case). Other control signals are set to 0 since this instruction doesn't involve reading from memory, branching, or writing to the register file. PCSrc is set to 0 because the next instruction's address is PC + 4 (no branching). b. [ 15 Points ] Please discuss what is the role of the “Imm Gen” in the non-pipelined Datapath above when executing the 3 instructions from Question (a) by answering (1) what “Imm Gen” does and why we need it ; and (2) for each of the 3 instructions . What is the specific input to “Imm Gen” and what is the specific output. The "Imm Gen" (Immediate Generator) in the non-pipelined Datapath is responsible for generating the immediate values required by instructions. It takes the 32-bit instruction and extracts the immediate field. Lw x9, 28(x23): Input to "Imm Gen": The 32-bit instruction containing the immediate field (28 in this case). Specific Output: The immediate value is 28, which is used for the memory address calculation. addi x9, x9, -5: Input to "Imm Gen": The 32-bit instruction containing the immediate field (-5 in this case). Specific Output: The immediate value is -5, which is used for the immediate addition. sw x9, 36(x22): Input to "Imm Gen": The 32-bit instruction containing the immediate field (36 in this case). Specific Output: The immediate value is 36, which is used for the memory address calculation. The "Imm Gen" is necessary to extract and provide the immediate values required by instructions for address calculations or immediate arithmetic operations. c. [ 15 Points ] Now we execute the 3 instructions from Questions (a) in the 5 - stage pipelined Datapath without forwarding hardware . Please (1) fill out the pipelined table; (Please use 1

F,D,X,M, and W to represent the 5 pipeline stages and S to represent stalls.) and (2) discuss what relative performance is compared to executing the 3 instructions on the non- pipelined datapath. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lw x9, 28(x23) F D X M W addi x9 , x9, -5 S S F D X M W sw x9 ,36(x22) S S F D X M W Performance: In a 5-stage pipelined Datapath without forwarding hardware, instructions can overlap in execution, but hazards such as data hazards may still lead to stalls, affecting performance. Execution in the 5-Stage Pipelined Datapath without Forwarding Hardware: In a 5- stage pipelined Datapath without forwarding hardware, each stage represents a different step in instruction execution: IF (Instruction Fetch), ID (Instruction Decode), EX (Execution), M (Memory Access), and W (Write Back). Instructions move through these stages sequentially. The performance improves compared to the non-pipelined Datapath as instructions overlap in execution, but data hazards may still lead to stalls. d. [ 25 Points ] Now we execute the 3 instructions from Question (a) in the 5-stage pipelined datapath with forwarding hardware . Please (1) fill out the pipelined table; (Please use F, D,X,M, and W to represent the 5 pipeline stages and S to represent stalls.) (2) discuss what hazards, if any, have and have not been eliminated as compared to Questions (c) the reasons; (3) discuss what hazards, if any, still exist and the reason why; and (4) discuss what relative performance is compared to executing the instructions on the non-pipelined Datapath. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lw x9, 28(x23) F D X M W addi x9 , x9, -5 S F D X M W sw x9 ,36(x22) F D X M W Hazard Elimination: Forwarding hardware can eliminate some hazards by forwarding data directly from the execution stage to earlier stages that need it, reducing the need for stalls. Hazard Existence: Structural hazards may still exist, such as resource conflicts for memory access. Control hazards may still lead to stalls due to branches or jumps. Relative Performance: With forwarding hardware, the pipeline operates more efficiently, reducing the impact of data hazards. However, performance can still be affected by structural and control hazards. Overall, it improves performance compared to the non-pipelined Datapath but may not completely eliminate all delays.

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