ECE668 Quiz3

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Florida Polytechnic University *

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5741

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Computer Science

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Feb 20, 2024

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Question 1 Correct Which of the following statements about MIPS are TRUE? Lo pens et . - : . ¥ Fisg question 1) Relative addressing is used rather than direct addressing. One reason for e this is we can have flexibility in where we can put programs in memory. 2) Relative addressing is used rather than direct addressing. One reason for this is fewer bits can be dedicated to the address field. Select one: a Bothiand2 v b. 1only ¢ 20nly d. Neither 1 nor 2 Your answer is correct. If we use direct addressing, we will need to specify the full memory address (which requires more bits) rather than just a relative displacement. Further, we will have to start our programs at a specific memory location and will not be able to move it, which is obviously undesirable. The correct answer is: Both 1.and 2 /| Question 2 Corect Which of the following are false statements about the instruction set of the MIPS processor? bt Lo ¥ Fiag question Select one or more: 2. The offset field in conditional branch instructions is signed extended before being added. b. The Op. Code field is 6 bits long and as a result, the MIPS instruction set includes 64 instructions. v ¢ The immediate field in an ALUi instruction s always extended to 32 bits by adding 16 1s in the high order positions. v d. AlIMIPS instructions use all the 32 bits in their format. v Your answer is correct. The FUNC field in the ALU format allow more than 64 instructions. JR, for example, uses only 11 out of the 32 bits. Every 16-bit operand (data or address) must be extended to 32 bits before being added to a 32-bit operand. True only if the 16-bit operand is negative, i.e., its most significant bit is 1. In general, higher order 16 bits should be sign extended. The correct answers are: The Op. Code field is 6 bits long and as a result, the MIPS instruction set includes 64 instructions., The immediate field in an ALUi instruction is always extended to 32 bits by adding 16 1s in the high order positions., All MIPS instructions use all the 32 bits in their format. /| Question3 Corect <eli : ifod i : f : : : 1000 poins outof A 5-stage pipeline has a single unified instruction and data memory capable of performing a single Read or Write operation oo every clock cycle. Assume that 34% of the executed instructions are Loads and 27% are Store. Ignoring any data hazards ¥ Flag question and control hazards that may occur, what is the speedup of the pipeline that has separate instruction and data memories over the pipeline with a single unified memory? (Round to two decimal places) Answer: 161 v Each Load and Store instruction will result in a single stall cycle in the original pipeline with unified memory. However, in the design with separate instruction and data memories, there would not be any stalls The correct answer is: 1.61

—_———— Question 4 A 5-stage pipeline has a Register File that can execute either a Read operation (of 1 or 2 registers) or a Write operation (into only one register), but not both, during every clock cycle. The instruction mix that the processor executes contains 39% ALU, 25% Load, 10.2% Store and the rest Branch instructions. Ignoring any data hazards and control hazards that may occur, what is the speedup of the pipeline that has a Register File capable of performing two reads and one write every cycle over the pipeline with the limited Register file? (Round to two decimal places) Answer: 1.64 v Every ALU or Load instruction that write into the Register Files will stall the pipeline by one cycle, due to the Structural Hazard, The correct answer is: 1.64 The only instruction in the 5-stage pipelined MIPS that needs all 5 stages, is Load. It has been suggested to design a 4- stage pipeline where the 4th stage will allow either a memory (read or write) operation, or a Register File write. The Load instruction will then be replaced by two instructions: Load-A (read from memory) and Load-B (write into the register file). The instruction mix that the processor executes contains 26% ALU instructions, 15% Load, 25% Store and the rest Branch. Ignoring all hazards and assuming that the two pipelines will have the same cycle time, what is the speedup of the 5-stage pipeline over the 4-stage one? (Round to two decimal places) Answer: 115 v The CPI of the two pipelines is the same (i.e,, 1) but the number of instructions for the 4-stage pipeline will increase by 15%. The correct answer is: 1.15 Increasing the number of the general-purpose registers in MIPS from 32 to 64 will reduce the range of immediate operands by a factor of Select one: 2, 2 b. 4 c 8 None of the above o Your answer is correct. An ALU instruction with an immediate operand has two register field that would need 12 instead of 10 bits reducing the range of the immediate operand by a factor of 4 The correct answer is: 4 Correct 100 points out of 1000 ¥ Flag question Question 5 Correct 1000 points out of 1000 ¥ Fiag question Question 6 Correct 10,00 points out of 1000 ¥ Flag question

Question 7 Correct If the MIPS and MFLOPS ratings of processor X when executing the SPEC benchmark “"equake" are both higher than the el Lot ratings of processor Y for the same benchmark then processor X will execute any other benchmark faster than processor Y. ¥ Fiag question Select one: a. True only if the same inputs to the benchmark are used when executing it on the two processors b. False only if different inputs to the benchmark are used when executing it on the two processors c True d. False v Your answer is correct. The correct answer is: False Y | o Comect The numbers (addresses) assigned to the floating-point registers in a processor must be different from those assigned to et the integer (general- purpose) registers. ¥ flag question Select one: a. Yes, they must be different b. No, they do not have to be different v Your answer is correct. The addresses for the floating point registers do not need to be different from the integer registers (actually they're better be the same), however, they will be recognized by the instruction op-code and will have their own RF. The correct answer is: No, they do not have to be different | Question 9 Correct Which of the following are false statements? B ¥ Flag question Select one or more: . Only the Load and Store instructions in MIPS perform address calculation. ¥ Branch instructions also perform address calculations. b. Some MIPS instructions use less than 16 out of the available 32 instruction bits. . The IF/ID and ID/EX inter-stage registers in the MIPS processor include the same number of ¥ For example, IF/ID includes register numbers (5-bit IDs) while ID/EX includes registers’ bits. content (32-bit data). Branch and Jump also include address calculation. JR uses 11 bits, d. None of the Above Your answer s correct. The correct answers are: Only the Load and Store instructions in MIPS perform address calculation,, The IF/ID and ID/EX inter-stage registers in the MIPS processor include the same number of bits. _ Question 10 Corect A program running on a non-pipelined processor executes 26% load instructions (5 cycles), 25% store instructions (4 stk cycles), 17% branch instructions (3 cycles) and the rest ALU instructions (4 cycles). What is the CPI? ¥ Flag question Answer: 4.09 v The correct answer is: 4.09

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