Prb4_Sp2024

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Computer Science 605.611 Problem Set 4 1. (5) The nine instructions that make up our MIPS core instruction subset are listed in the table below. The table also shows the time required to fetch and execute each of these nine instructions on a certain implementation of the single cycle data path. Instruction Time required to fetch and execute add, sub, slt, and, or 50ns per instruction lw 100ns sw 90ns beq 70ns j 50ns What is the maximum clock rate that can be used for this implementation of the single cycle data path? Express your answer in MHz. 2. (3) The ALU within the single-cycle datapath outputs a 32-bit data result (R31, R30, … , R1, R0) along with a single-bit zero flag (ZERO). Write down a logic expression that gives ZERO as a logic function of the 32-bit result. ZERO = _____________________________________ 3. The MIPS addu instruction performs the same operation as the MIPS add instruction. The only difference is that add triggers an exception if the addition results in a signed overflow, while addu does not. The instruction addu $4, $5, $6 places into register $4 the 32-bit sum of the contents of register $6 plus the contents of register $5. Answer the following questions about the instruction addu $4, $5, $6 : a) (3) If registers $5 and $6 contain integers that differ in sign, can the result in $4 be incorrect due to an overflow? Explain your answer. b) (3) If an overflow does not occur and registers $5 and $6 both contain a negative integer, what will be the sign of the result in $4? c) (3) If an overflow does occur and registers $5 and $6 both contain a positive integer, what will be the sign of the result in $4?

4. The lw, sw and beq MIPS instructions all use the low 16-bits within the machine instruction together with a base register to generate a 32-bit memory address. a) (3) Identify the bits within the 32-bit sw machine instruction that indicate the base register to use to generate the 32-bit memory address? The instruction bits are numbered 0 to 31 from right to left. b) (3) Explain how the 32-bit lw machine instruction uses the low 16 bits from the instruction to generate the 32-bit memory address. c) (3) Explain how the 32-bit beq machine instruction uses the low 16 bits from the instruction to generate the 32-bit branch target address. This was explained in module 1 as well as in appendix A of the textbook. d) (3) Explain how the 32-bit j (jump) machine instruction generates the 32-bit address to which the instruction transfers control. This was explained in module 1 as well as in appendix A of the textbook. 5. Listed below are three of the possible patterns for the 2-bit ALUOp control. Indicate what operation the ALU performs for each of these 2-bit patterns. a) (3) 01 b) (3) 10 c) (3) 00

6. The format of each MIPS machine instruction defines how many separate fields the 32-bit machine instruction contains as well as the width in bits of each field. The instruction opcode determines the machine instruction format (R-type, I-type or J-type). Specify the number of fields and the width of each field within each machine instruction whose opcode is shown below. Base your answes on our MIPS core 9-instruction subset. a) (3) 000100 b) (3) 000000 c) (3) 000010 d) (3) 101011 7. (5) Identify the control bits within the single-cycle data path that are used to decide whether the beq instruction should transfer control and explain how the transfer is performed.

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8. (5) The diagram below shows a logic gate implementation of a device that accepts a single control bit C along with 4 data inputs N3 through N0. The device outputs 8 bits X7 through X0. Complete the table below to show the X outputs generated by the device in response to the C and N inputs shown below. Indicate 0 or 1 for each of the output bits X7 through X0. C N3 N2 N1 N0 X7 X6 X5 X4 X3 X2 X1 X0 0 1 0 1 1 1 1 1 1 0

8. All MIPS opcodes are 6 bits in size and each opcode can be represented as two hex digits. The circuit shown below is one option for generating the 9 control bits required to implement an instruction on the single-cycle datapath. For each of the instructions listed below show the 2- digit hex number that corresponds to the required 6 input bits (Op5 through Op0) and the 3-digit hex number that corresponds to the 9 output control bits that should be output for each set of 6 input bits. a) (3) beq input= ____ output = ____ b) (3) lw input= ____ output = ____ c) (3) or input= ____ output = ____ d) (3) add input= ____ output = ____ 9. (7) Some MIPS instructions use the low 16 bits within the machine instruction as a displacement or immediate operand. For each of the instructions listed below, explain whether the instruction uses a 16-bit displacement or immediate operand and whether it sign-extends or zero-extends the 16-bit value. jr addiu addi ori lui andi j

10. Reproduced below is one version of the MIPS single-cycle data path diagram discussed in module 4. For each of the following instructions, indicate whether this data path, as shown, DOES or DOES NOT support the instruction. Explain your answer in each case. a) (3) and b) (3) lw c) (3) j d) (3) beq e) (3) jr

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11. (6) Our “MIPS core instruction subset” is defined as the following group of instructions: add, sub, and, or, slt, lw, sw, beq & j . List all of the control bits required for this MIPS core instruction subset on the single-cycle datapath and explain the purpose of each control bit.

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