Programmable Logic Controllers
Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
Question
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Chapter 8, Problem 7P
Program Plan Intro

Count-Up (CTU) Counter:

  • The CTU counter refers to an up counter
  • This counter is used to count an event that occurs logically or externally and places that value in the counter’s accumulator.
  • The accumulated value can even be maintained during false rung conditions and can be reset back to 0 using reset instruction.

Count-Down (CTD) Counter:

  • The CTD counter refers to a down counter
  • It decrements the accumulated value at each false-to-true transition and it also retains the accumulated value as soon as an on/off power cycle occurs.

Explanation of Solution

b.

Accumulated count of counter CTD:

  • It is given that 20 on/off transitions occur at input “A” and 5 on/off transitions occur at input “B”.
  • The CTU and CTD counters are addressed at the same location “C5:2”.
  • The up-counter and down-counter operates simultaneously to increment and decrement the accumulated count value...

Explanation of Solution

c.

State of output A:

  • Here, the accumulated count value of CTU counter is 15.
  • The output “A” gets activated only when it receives CU signals from the counter “C5:2”.
  • But, the preset value is set for 10...

Explanation of Solution

d.

State of output B:

  • Here, the accumulated count value of CTD counter is 15.
  • The output “B” gets activated only when it receives CD signals from the counter “C5:2”.
  • But, the preset value is set for 10...

Explanation of Solution

e.

State of output C:

  • Here, the accumulated count value of up/down counters is 15 and it is greater than the preset value 10 in the counters addressed at “C5:2’...

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⚫ your circuit diagrams for your basic bricks, such as AND, OR, XOR gates and 1 bit multiplexers, ⚫ your circuit diagrams for your extended full adder, designed in Section 1 and ⚫ your circuit diagrams for your 8-bit arithmetical-logical unit, designed in Section 2. 1 An Extended Full Adder In this Section, we are going to design an extended full adder circuit (EFA). That EFA takes 6 one bit inputs: aj, bj, Cin, Tin, t₁ and to. Depending on the four possible combinations of values on t₁ and to, the EFA produces 3 one bit outputs: sj, Cout and rout. The EFA can be specified in principle by a truth table with 26 = 64 entries and 3 outputs. However, as the EFA ignores certain inputs in certain cases, it is easier to work with the following overview specification, depending only on t₁ and to in the first place: t₁ to Description 00 Output Relationship Ignored Inputs Addition Mode 2 Coutsjaj + bj + Cin, Tout= 0 Tin 0 1 Shift Left Mode Sj = Cin, Cout=bj, rout = 0 rin, aj 10 1 1 Shift Right…
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