Electric Circuits. (11th Edition)
11th Edition
ISBN: 9780134746968
Author: James W. Nilsson, Susan Riedel
Publisher: PEARSON
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Chapter 8, Problem 56P
a.
To determine
Find the expression of
b.
To determine
Calculate the time taken by the inductor after the switch opens to attain its maximum voltage.
c.
To determine
Find the maximum value of the inductor voltage.
d.
To determine
Find the expression of
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3) In the ideal autotransformer circuit shown below find 11, 12 and lo. Find the average power delivered to the
load. (hint: write KVL for both sides)
20/30° V(+
2-1602
200 turns
V₂
10 + j40 Ω
80 turns
V₁
11-2)
Now consider that white noise (i.e., noise with a PSD that is constant with frequency) is introduced in the channel of
the system described in the previous problem. An ideal low pass filter is used at the receiver input to reduce the noise
as much as possible, while transmitting the desired signal.
(a) By what factor should the cutoff frequency of the noise reduction filter be reduced in the 16-PAM case, compared
to binary?
(b) By what factor will the noise power at the decision circuit be reduced in the 16-PAM case?
(c) By what factor will the noise amplitude at the decision circuit be reduced in the 16-PAM case?
(d) To obtain the same symbol error rate for 16-PAM as for binary, how should the minimum level spacing for
16-PAM compare to binary?
(e) If the 16-PAM level spacing is adjusted according to part (d) above, by what factor will the average signal power
be increased in the 16-PAM case, compared to binary?
Chapter 8 Solutions
Electric Circuits. (11th Edition)
Ch. 8.1 - The resistance and inductance of the circuit in...Ch. 8.2 - Use the integral relationship between iL and v to...Ch. 8.2 - Prob. 3APCh. 8.2 - Prob. 4APCh. 8.2 - Prob. 5APCh. 8.3 - Prob. 6APCh. 8.4 - Prob. 7APCh. 8.4 - Prob. 8APCh. 8.4 - Repeat Assessment Problems 8.7 and 8.8 if the 80 Ω...Ch. 8 - The resistance, inductance, and capacitance in a...
Ch. 8 - Prob. 2PCh. 8 - Prob. 3PCh. 8 - Prob. 4PCh. 8 - Prob. 5PCh. 8 - Prob. 6PCh. 8 - The natural response for the circuit shown in Fig....Ch. 8 - The natural voltage response of the circuit in...Ch. 8 - The voltage response for the circuit in Fig. 8.1...Ch. 8 - Prob. 10PCh. 8 - Design a parallel RLC circuit (see Fig. 8.1) using...Ch. 8 - Prob. 12PCh. 8 - The initial value of the voltage υ in the circuit...Ch. 8 - Prob. 14PCh. 8 - The resistor in the circuit of Fig. P8.14 is...Ch. 8 - Prob. 16PCh. 8 - The switch in the circuit of Fig. P8.17 has been...Ch. 8 - The inductor in the circuit of Fig. P8.17 is...Ch. 8 - The inductor in the circuit of Fig. P8.17 is...Ch. 8 - Prob. 20PCh. 8 - Prob. 21PCh. 8 - Prob. 22PCh. 8 - Prob. 23PCh. 8 - Prob. 24PCh. 8 - Prob. 25PCh. 8 - Prob. 26PCh. 8 - The switch in the circuit in Fig. P8.27 has been...Ch. 8 - For the circuit in Fig. P8.27, find υo for t ≥...Ch. 8 - The switch in the circuit in Fig. P8.29 has been...Ch. 8 - There is no energy stored in the circuit in Fig....Ch. 8 - For the circuit in Fig. P8.30, find υo for t ≥...Ch. 8 - Prob. 32PCh. 8 - Prob. 33PCh. 8 - Prob. 34PCh. 8 - Switches 1 and 2 in the circuit in Fig. P8.35 are...Ch. 8 - The switch in the circuit in Fig. P8.36 has been...Ch. 8 - Prob. 37PCh. 8 - Prob. 38PCh. 8 - In the circuit in Fig. P8.39, the resistor is...Ch. 8 - The initial energy stored in the 50 nF capacitor...Ch. 8 - Prob. 41PCh. 8 - Find the voltage across the 80 nF capacitor for...Ch. 8 - Design a series RLC circuit (see Fig. 8.3) using...Ch. 8 - Change the resistance for the circuit you designed...Ch. 8 - Prob. 45PCh. 8 - Prob. 46PCh. 8 - Prob. 47PCh. 8 - The switch in the circuit shown in Fig. P8.48 has...Ch. 8 - Prob. 49PCh. 8 - The initial energy stored in the circuit in Fig....Ch. 8 - The resistor in the circuit shown in Fig. P8.50 is...Ch. 8 - The resistor in the circuit shown in Fig. P8.50 is...Ch. 8 - The two switches in the circuit seen in Fig. P8.53...Ch. 8 - Prob. 54PCh. 8 - Prob. 55PCh. 8 - The circuit parameters in the circuit of Fig....Ch. 8 - Prob. 57PCh. 8 - Prob. 58PCh. 8 - Prob. 59PCh. 8 - Prob. 60PCh. 8 - Prob. 61PCh. 8 - Derive the differential equation that relates the...Ch. 8 - The voltage signal of Fig. P8.63(a) is applied to...Ch. 8 - The circuit in Fig. P8.63 (b) is modified by...Ch. 8 - Prob. 65PCh. 8 - Prob. 66PCh. 8 - Prob. 67PCh. 8 - Prob. 68P
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- 11-1) similar to Lathi & Ding, Prob. P.6.7-5 Data at a bit rate Rb must be transmitted using either binary NRZ polar signaling or 16-ary PAM NRZ polar signaling. (a) By what factor will the symbol rate be reduced in the 16-PAM case? (b) By what factor will bandwidth required from the (lowpass) channel be reduced in the 16-PAM case? (c) Assuming the minimum spacing between pulse levels must be the same in both cases, by what factor will the average power be increased in the 16-PAM case? [Hint: take the pulse amplitudes to be ±A in the binary case, and ±A, ±3A, ±5A,..., ±154, and recall that scaling pulse amplitude by a factor k scales the pulse energy by a factor R². Assume that the data is random, so that all 16 levels are equally likely, and that the same pulse shape is used in both cases.] Warning: Solutions to the textbook problem that are posted online are mostly wrong. Work it out for yourself.arrow_forward11-3) similar to Lathi & Ding, Prob. P.6.8-1 Consider the carrier modulator shown in the figure below, which transmits a binary carrier signal. The baseband generator uses polar NRZ signaling with rectangular pulses. The data rate is 8 Mbit/s. (a) If the modulator generates a binary PSK signal, what is the bandwidth of the modulated output? (b) If the modulator generates FSK with the difference fel - fco = 6 MHz (cf. Fig 6.32c), determine the modulated signal bandwidth. Binary data source Baseband signal generator Modulated output Modulator N-E---arrow_forwardFor the circuit shown, find (i) closed-loop voltage gain (ii) Z i of the circuit (iii) f_max. The slew rate is 0.6V/us. ((write your answer in Kilo ohm)) 2Vpp R ww 20 kQ R₁ ww 200 ΚΩ 9+18 V - 18 V 10 kn R₁₂ ΚΩ ((write your answer in KHz))arrow_forward
- illustrate the phenomenon of phase reversal in CE amplifier i- When signal current =OA, so IB-8uA ii- When input signal reaches positive peak, so IB=16uA ii- When input signal reaches negative peak, so IB=4uA R₁ www + Vcc = 12V Rc=6kn 16 A 8 μA 4 μА 0 www RE ẞ = 100 VCarrow_forwardIn the circuit shown, find the voltage gain. Given that ẞ = 80 and input resistance Rin=2kQ. SIGNAL +10 V Rc=6kn 4-2 210arrow_forwardFor the transistor amplifier shown, R₁-11kQ, R2=6kQ, Rc=2kQ, RE-3kQ and R₁=2k0. (i) Draw d.c. load line (ii) Determine the DC operating point (iii) Draw a.c. load line. Assume V_BE = 0.7 V. and determine the new operating point + Vcc = 15 V RC Cc Cin R1 wwwwww wwwww R₁₂ RE CE RLarrow_forward
- the first part is the second part write your answer such as: (AND, OR, INVERTER, NAND, NOR) D₁ AK D, R₁ B K First Part? the third part is , and the total are R4 R7 Output R5 R₁ T R6 R3 -UBB Second Part? Third Part? Total?arrow_forwardA multistage amplifier has six stages each of which has a power gain of 40. what is the - Total gain of the amplifier in db ? ii- If the negative feedback of 15db is employed, find the resultant gainarrow_forward9.36 Consider the finite-state machine logic implementation in Figure P9.36. (a) Determine the next-state and output logic expressions. (b) Determine the number of possible states. J1 Clk K₁ 101 Ут J2 Clk K₂ Clk Figure P9.36 0 y2 10arrow_forward
- 9.34 Consider the finite-state machine logic implementation in Figure P9.34. (a) Determine the next-state and output logic expressions. (b) Determine the number of possible states. (c) Construct a state assigned table. (d) Construct a state table. (e) Construct a state diagram. (f) Determine the function of the finite-state machine. T₁ x Clk Figure P9.34 Q Clk Q الا T₂ Q 32 Clk Q T3 Q Clk Q Узarrow_forward9.35 Consider the finite-state machine logic implementation in Figure P9.35. (a) Determine the next-state and output logic expressions. (b) Determine the number of possible states. (c) Construct a state assigned table. (d) Construct a state table. (e) Construct a state diagram. (f) Determine the function of the finite-state machine. Clk J Clk K₁ 10 Ут J2 Clk K₂ 10 32 Figure P9.35arrow_forward9.56 Using JK flip-flops, design a synchronous counter that counts in the sequence 1, 3, 0, 2, 1, ... The counter counts only when its enable input x is equal to 1; otherwise, the counter is idle.arrow_forward
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