Chapter 5, Problem 5.7.4E

Explanation of Solution

Given:

Processor speed = $\text{2GHz}$

Main memory access time = $\text{100ns}$

First-level cache miss rate = $\text{7\%}$

Second-level cache = $\text{12 cycles}$

Second-level cache miss rate = $\text{3}\text{.5\%}$

Third-level cache = $\text{50 cycles}$

Base CPI = $\text{1}\text{.5}$

Second-level 8-way set associative access = $\text{28 cycles}$

Global miss rate with second-level 8-way set associative access = $\text{1}\text{.5\%}$

Calculation:

$\begin{array}{l}\text{Memory miss cost = Processor speed + Main memory access}\\ \text{ = }\left(\text{2 }\times {\text{ 10}}^9\right)\times \left(\text{100 }\times {\text{ 10}}^{-9}\right)\\ \text{ = 200 cycles}\end{array}$

Only a first-level cache in the system:

$\begin{array}{l}\text{First-level cache CPI = 1}\text{.5 + }\left(\text{0}\text{.07 }\times \text{ 200}\right)\\ \text{ = 1}\text{.5 + 14}\\ \text{ = 15}\text{.5}\end{array}$

Second-level direct-mapped cache:

L1 miss, L2 hit penalty = $\text{12 cycles}$

$\begin{array}{l}\text{Both miss penalty = 12 + 200}\\ \text{ = 212 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{second level cache }\times \text{ first level miss rate}\right)\text{ +}\\ \left(\text{memory miss cost × Second-level cache miss rate}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 7\%}\right)\text{ + }\left(\text{212 }\times \text{ 3}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 0}\text{.07}\right)\text{ + }\left(\text{212 }\times \text{ 0}\text{.035}\right)\\ \text{ = 1}\text{.5 + 0}\text{.84 + 7}\text{.42}\\ \text{ = 9}\text{.76}\end{array}$

Second-level 8-way set associative cache:

L1 miss, L2 hit penalty = $\text{28 cycles}$

$\begin{array}{l}\text{Both miss penalty = 28 + 200}\\ \text{ = 228 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{second level cache × penalty}\right)\text{ +}\\ \left(\text{memory miss cost × second-level 8-way set associative access}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 7\%}\right)\text{ + }\left(\text{228 × 1}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 0}\text{.07}\right)\text{ + }\left(\text{228 × 0}\text{.015}\right)\\ \text{ = 1}\text{.5 + 1}\text{.96 + 3}\text{.42}\\ \text{ = 6}\text{.88}\end{array}$

For double memory access time:

$\begin{array}{l}\text{Memory miss cost = 2 }\times \left(\text{Processor speed + Main memory access}\right)\\ \text{ = 2 }\times \left(\left(\text{2 }\times {\text{ 10}}^9\right)\times \left(\text{100 }\times {\text{ 10}}^{-9}\right)\right)\\ \text{ = 2 }\times \text{ 200 }\\ \text{ = 400 cycles}\end{array}$

Only a first-level cache in the system:

$\begin{array}{l}\text{First-level cache CPI = 1}\text{.5 + }\left(\text{0}\text{.07 }\times \text{ 400}\right)\\ \text{ = 1}\text{.5 + 28}\\ \text{ = 29}\text{.5}\end{array}$

Second-level direct-mapped cache:

L1 miss, L2 hit penalty = $\text{12 cycles}$

$\begin{array}{l}\text{Both miss penalty = 12 + 400}\\ \text{ = 412 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{second level cache }\times \text{ first level miss rate}\right)\text{ +}\\ \left(\text{memory miss cost × Second-level cache miss rate}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 7\%}\right)\text{ + }\left(\text{412 }\times \text{ 3}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 0}\text{.07}\right)\text{ + }\left(\text{412 }\times \text{ 0}\text{.035}\right)\\ \text{ = 1}\text{.5 + 0}\text{.84 + 14}\text{.42}\\ \text{ = 16}\text{.76}\end{array}$

Second-level 8-way set associative cache:

L1 miss, L2 hit penalty = $\text{28 cycles}$

$\begin{array}{l}\text{Both miss penalty = 28 + 400}\\ \text{ = 428 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{second level cache × penalty}\right)\text{ +}\\ \left(\text{memory miss cost × second-level 8-way set associative access}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 7\%}\right)\text{ + }\left(\text{428 × 1}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 0}\text{.07}\right)\text{ + }\left(\text{428 × 0}\text{.015}\right)\\ \text{ = 1}\text{.5 + 1}\text{.96 + 6}\text{.42}\\ \text{ = 9}\text{.88}\end{array}$

For half memory access time:

$\begin{array}{l}\text{Memory miss cost = }\frac{\left(\text{Processor speed + Main memory access}\right)}{2}\\ \text{ = }\frac{\left(\left(\text{2 }\times {\text{ 10}}^9\right)\times \left(\text{100 }\times {\text{ 10}}^{-9}\right)\right)}{2}\\ \text{ = }\frac{\text{200}}{2}\\ \text{ = 100 cycles}\end{array}$

Only a first-level cache in the system:

$\begin{array}{l}\text{First-level cache CPI = 1}\text{.5 + }\left(\text{0}\text{.07 }\times \text{ 100}\right)\\ \text{ = 1}\text{.5 + 7}\\ \text{ = 8}\text{.5}\end{array}$

Second-level direct-mapped cache:

L1 miss, L2 hit penalty = $\text{12 cycles}$

$\begin{array}{l}\text{Both miss penalty = 12 + 100}\\ \text{ = 112 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{second level cache }\times \text{ first level miss rate}\right)\text{ +}\\ \left(\text{memory miss cost × Second-level cache miss rate}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 7\%}\right)\text{ + }\left(\text{112 }\times \text{ 3}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 0}\text{.07}\right)\text{ + }\left(\text{112 }\times \text{ 0}\text{.035}\right)\\ \text{ = 1}\text{.5 + 0}\text{.84 + 3}\text{.92}\\ \text{ = 6}\text{.27}\end{array}$

Second-level 8-way set associative cache:

L1 miss, L2 hit penalty = $\text{28 cycles}$

$\begin{array}{l}\text{Both miss penalty = 28 + 100}\\ \text{ = 128 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{second level cache × penalty}\right)\text{ +}\\ \left(\text{memory miss cost × second-level 8-way set associative access}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 7\%}\right)\text{ + }\left(\text{128 × 1}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 0}\text{.07}\right)\text{ + }\left(\text{128 × 0}\text{.015}\right)\\ \text{ = 1}\text{.5 + 1}\text{.96 + 1}\text{.92}\\ \text{ = 5}\text{.38}\end{array}$