Chapter 5, Problem 23RETC

Explanation of Solution

Difference between Intel and MIPS:

Intel	MIPS
In this case the addressing architecture is two-addressing mode.	In this case the addressing architecture is word-addressable and three-address mode.
It uses instruction of variable length.	It uses instruction of fixed length.
Pipelining: the Pentium I contained two 5-stage pipelines. Stages were fetched in advance, instruction decode, address generation, execute, and write back. Pentium II contained 12-stage pipeline, Pentium III contained a 14-stage pipeline and Pentium IV contained a 24-stage pipeline.	Pipelining: R2000 and R3000 contain 5-stage pipelines. The R4000 and R4400 contain 8-stage superpipelines. In R10000, the number of pipeline stages depends on the functional unit through which the instruction must pass: 5stages for Integer, 6 stages for load/store, and 7 stages for floating point instructions...