Using D flip-flops, design a synchronous counter. The counter counts in the sequence 1,3,5,7, 1,7,5,3,1,3,5,7,.... when its enable input x is equal to 1; otherwise, the counter. This counter is for individual settings only need the state diagram and need the state table to use 16 states from So to S15.

: A sequential network has one input (X) and two outputs (Z1 and Z2). An output Z1 Z2 = 10 occurs every time the input sequence 1011 is completed. An output Z1 Z2 = 01 occurs every time the input sequence 0101 is completed. Otherwise Z1 Z2 = 0 Find Moore state diagram with minimum number of states: a) When overlap is allowed. b) When overlap is not allowed. I need a step by step printable solution that uses sequences on the same drawing.

1. Consider a negative unity-feedback control system whose plant transfer function is type- 1. Suppose you want to build a lead compensator so that -3 ± 5j are dominant poles. You observed that the angle deficiency at the desired dominant pole is 50°. Compute a 's+b' and b of the lead compensator (s+ 2) so that the error constant Ky is maximized. In other words, design the lead compensator in a way so that the steady-state error for ramp input is minimum