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Y₁ X1 Yo xo' [ D D 그 W

Y₁ X1 Yo xo' [ D D 그 W

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Problem 1 Y₁ X1 Yo Xo (a) Combinational circuit analysis Fill in the following truth table for C. x1 xoyi yo z w X1 X0 yi yo 0 0 0 0 1000 1001 1010 101 1 1100 1101 1 1 10 1111 0001 0010 0 0 1 1 0100 0101 0110 0 1 1 1 Z W W The inputs of this arithmetic circuit C are two 2-bit unsigned binary numbers X = xixo and Y = yiyo. It is intended to compute three output bits g. 1, and e, defined as follows. g=1 if X>Y, 1=1 if X<Y, and e = 1 if X = Y. For example, if X=11 denoting "3" and Y = 10 denoting "2", then the output should be gle = 100. However, the design is incomplete, and C only generates two of the desired outputs, which are denoted w and z in the figure. (b) Determine the correspondence between w,z and two of the three target outputs g,1,e. In other words, which of g.l,e is z, and which is w? (c) Let v denote the third target output which is missing from the figure. Using as few gates of the AND, OR, and NOT type as you can, and without deleting any gates from the given circuit C, add the logic needed to compute v.
Transcribed Image Text:Problem 1 Y₁ X1 Yo Xo (a) Combinational circuit analysis Fill in the following truth table for C. x1 xoyi yo z w X1 X0 yi yo 0 0 0 0 1000 1001 1010 101 1 1100 1101 1 1 10 1111 0001 0010 0 0 1 1 0100 0101 0110 0 1 1 1 Z W W The inputs of this arithmetic circuit C are two 2-bit unsigned binary numbers X = xixo and Y = yiyo. It is intended to compute three output bits g. 1, and e, defined as follows. g=1 if X>Y, 1=1 if X<Y, and e = 1 if X = Y. For example, if X=11 denoting "3" and Y = 10 denoting "2", then the output should be gle = 100. However, the design is incomplete, and C only generates two of the desired outputs, which are denoted w and z in the figure. (b) Determine the correspondence between w,z and two of the three target outputs g,1,e. In other words, which of g.l,e is z, and which is w? (c) Let v denote the third target output which is missing from the figure. Using as few gates of the AND, OR, and NOT type as you can, and without deleting any gates from the given circuit C, add the logic needed to compute v.
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