write VHDL code to implement a 4-bit adder of figure below. The circuit has two inputs (a, b) and one output (sum). All signals are of type SIGNED. a (3:0) + sum (4:0) b (3:0)
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- Given a 4-bit signed integer, design a circuit that outputs its absolute value. You can assume that the input will always have a valid output. (a) Draw a logic diagram of this circuit. You may use 4-bit half adder(s), 2x1 4-bit multiplexer(s), and any logic gate(s) in your design. (b) With the following Verilog code, implement your design above in Verilog. module half_adder (input [3:0] a, input [3:0] b, output [3:0] s); assign s = a + b; endmodule module mux(input [3:0] D0, input [3:0] D1, input S, output reg [3:0] O); always @(*) begin if (S == 0) O = D0; else if (S == 1) O = D1; else O = 4’bx; end endmoduleQuestion 2: A combinational circuit has 4 inputs (A, B, C, D) and 1 output (F). ABCD represent a majority function. The output of the majority function is equal to 1 if the input variables have more 1's than O's, otherwise the output is 0. a. Construct the truth table of the required circuit. b. Implement the minimized expression of F using 3-level all NAND gate circuit. Implement a 2-1Multiplexer using three-state buffers.Implement the following Boolean function with an 8–to–1-line multiplexer and a single inverter with variable D as its input: F(A, B, C, D) = Σm(2, 4, 6, 9, 10, 11, 15)
- Design a circuit with a 4-bit BCD input A, B, C, D that produces an output W, X, Y, Z that is equal to the input + 3 in binary. For example, 9 (1001) + 3 (0011) = 12 (1100). The outputs for invalid BCD codes are don’t-cares. Write the truth table and the Karnaugh maps used to simplify the Boolean expression!Design a circuit that uses 4-bit full adders and AND gates. Given two 8-bit signed 2s-complement numbers A and B and a binary input signal M, your circuit should produce an 8-bit signed 2s-complement result R, as follows: if (M == 0) R = A; else R = A + B + 1;a. Draw a circuit which produces Sum and CarryOut from inputs A and B (this circuit is known as a half adder). You should use exactly one AND gate and one XOR (exclusive or) gate. b. Give the truth table for a full adder (which incorporates a carry-in bit to the sum of A and B):
- Design a code converter that converts an unsigned number a into its negative 2's complement representation -a. Specifically, the circuit has two inputs: a1 and ao, and three outputs: b1 and bo (the equivalent to -a) and valid, which is 1 when -a can be represented in 2's complement and O otherwise. 1. Write the truth table for the code converter. 2. Give the simplest SOP expressions for the functions b1, bo, and valid.Design a 16 bit adder/subtractor with 2 data inputs (B15 to B0 and A15 to A0), a SEL input (1 if add and 0 if subtract), and a result output (R15 to R0).You can design the circuit in MultiSim, VHDL, or LabVIEW. PLEAE USE MULTISIMUse VHDL to implement a 16-to-1 Multiplexer. The inputs are w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, and w11. The last four inputs are not attached to an input signal. How many select bits need the circuit?
- stion : 1/1 a Implement the function F (A, B, C) = E(1, 2, 4, 5, 7) a. Using a 2x4 decoder and any logic gates. b. Using a 4:1 multiplexer. P Type here to search 60Design a combinational circuit that increments the 4-bit binary input. The output of the circuit is also represented as 4 bits. For example, if the input is 0011 then the output is 0100. Note: the increment of 1111 is 0000. Let the input variables be A, B, C, and D, while the output variables be W, X, Y, and Z. What is the boolean function (in sum of minterm format) of output W? What is the boolean function (in sum of minterm format) of output X? What is the boolean function (in sum of minterm format) of output Y? What is the boolean function (in sum of minterm format) of output Z?Draw a 4-bit decrement circuit (subtracts 1 (i.e., z = x − 1)) that does not use not gates.