wiww!ww 10 V 4 OV 10 Ω 10 Ω 10 Ω FIGURE P23.62

E(t)=u(t) num(z) 20 den(z) $2+9s+20 Zero-Order Hold Digital Controller Plant Y(t) Fig. 2 A closed-loop sampled-data system with digital controller 2. Consider the closed-loop sampled-data system that is given in Fig. 2. a) Design a unity-dc-gain phase-lag compensator that yields a phase margin of 45 degree. Use ww1 = 10.6 rad/sec. b) Start simulink and construct the model that is given in Fig.2. Additionally, in order to plot the Y(t) by using workspace use a clock and a workspace blocks which are named as t, ytSampled. Set the sampling time -1 for all workspace blocks. Use the result of e for Digital Controller. Select an appropriate time for simulation and run it by clicking on the start button. Plot the Y(t) by using t and ytSampled. c) Plot the Bode diagram of this system and determine the phase and gain margin. d) Repeat a, b and c for ww₁ = 23 rad/sec and ww₁ = 83.6 rad/sec. e) Discuss the effect of the phase-lead compensator for different w₁values (Hint: Consider both the…