*timescale Ins / lpsmodule mux (input I0, Il, slct, output out);wire slct n;wire out_l;wire out_2;not (slct_n, slct);and (out_1, IO, slct_n);and (out_2, Il, slct);or (out, out_1, out_2);endmodule'timescale Ins / lpsmodule testbench ();reg 10, I1, slct;wire out;integer i;mux dt (.10 (I0), .Il (Il), .slct (slct), .out (out));initial begin10=0; Il=0; slct=0;Smonitor ("slct=%0b 10=$0b Il=%0b out=30b",slct,I0, I1, out);for (i=0; i<8; i=i+l)begin{slct, 10, I1}=i; #10;endendinitial#80 $finish;endmoduleWhich of the following is true for the above 2verilog codes?I. Gate design level is used in the code.II. 2x1 Multiplexer is designed in the code.II. All nets in the codes must be defined in the"testbench" section.

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Which of the following is true for the above 2 verilog codes? Gate design level is used in the code. 2x1 Multiplexer is designed in the code. All nets in the codes must be defined in the "testbench" section.

Which of the following is true for the above 2 verilog codes? Gate design level is used in the code. 2x1 Multiplexer is designed in the code. All nets in the codes must be defined in the "testbench" section.

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Chapter1: Introduction

Section: Chapter Questions

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Question

*timescale Ins / lps
module mux (input I0, Il, slct, output out);
wire slct n;
wire out_l;
wire out_2;
not (slct_n, slct);
and (out_1, IO, slct_n);
and (out_2, Il, slct);
or (out, out_1, out_2);
endmodule
'timescale Ins / lps
module testbench ();
reg 10, I1, slct;
wire out;
integer i;
mux dt (.10 (I0), .Il (Il), .slct (slct), .out (out));
initial begin
10=0; Il=0; slct=0;
Smonitor ("slct=%0b 10=$0b Il=%0b out=30b",slct,I0, I1, out);
for (i=0; i<8; i=i+l)begin
{slct, 10, I1}=i; #10;
end
end
initial
#80 $finish;
endmodule
Which of the following is true for the above 2
verilog codes?
I. Gate design level is used in the code.
II. 2x1 Multiplexer is designed in the code.
II. All nets in the codes must be defined in the
"testbench" section.

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