Which are conditions that can cause a FF to go metastable? (Mark all that apply.) O a. When the input signal changes after the clock with less time than the FF hold time. O b. When the input signal changes before the clock with less time than the FF set-up time. Oc. When the input signal changes before the clock with more time than the FF set-up time. O d. When the input signal changes before the clock with more time than the FF hold time. O e. When the input signal changes before the clock and after the clock, with more time than the FF set-up and hold times respectively. QUESTION 10 The simplification strategy used in the Karnaugh Map is based on which of the following Boolean Logic Theorems (Assume notation ( IA) means (NOT A). O a. (A"B) = IA + /B O b. A+ IAB = A +B O C. AB + A/B =A O d. AB + /AC + BC = AB + /AC e (A+B) = /A* /B QUESTION 11 Which of the following are types or variations of FSMS mentioned in class? (Mark all that apply) O a. Timed FSM. O b. None of the above. OC. Recursive FSM. O d. Basic FSM. De. Interacting FSMS.

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QUESTION 9
Which are conditions that can cause a FF to go metastable? (Mark all that apply.)
O a. When the input signal changes after the clock with less time than the FF hold time.
O b. When the input signal changes before the clock with less time than the FF set-up time.
O c. When the input signal changes before the clock with more time than the FF set-up time.
O d. When the input signal changes before the clock with more time than the FF hold time.
O e. When the input signal changes before the clock and after the clock, with more time than the FF set-up and hold times respectively.
QUESTION 10
The simplification strategy used in the Karnaugh Map is based on which of the following Boolean Logic Theorems (Assume notation ( IA) means (NOT A).
O a. (A*B) = IA + /B
O b. A+ /AB = A + B
O C. AB + A/B = A
O d. AB + /AC + BC = AB + /AC
e (A+B) = /A /B
QUESTION 11
Which of the following are types or variations of FSMS mentioned in class? (Mark all that apply.)
O a. Timed FSM.
O b. None of the above.
O C. Recursive FSM.
O d. Basic FSM.
De. Interacting FSMS.
QUESTION 12
Which of the following are true for a Mealy type Finite State Machine. (Mark all that apply.)
O a. The values assigned to the Output signals are specified in the Transition branches between states
Ob. The VHDL model for Mealy uses a Process()
Output Decoder with only the State signal in the sensitivity list.
Oc. The values assigned to the Output signals are specified in a State Transition table, but not in the State Transition diagram
d. The VHDL model for Mealy uses a Process() for Output Decoder with the Input signals and the State signal on the sensitivity list.
De. The values assigned to the Output signals are specified inside the state
Transcribed Image Text:QUESTION 9 Which are conditions that can cause a FF to go metastable? (Mark all that apply.) O a. When the input signal changes after the clock with less time than the FF hold time. O b. When the input signal changes before the clock with less time than the FF set-up time. O c. When the input signal changes before the clock with more time than the FF set-up time. O d. When the input signal changes before the clock with more time than the FF hold time. O e. When the input signal changes before the clock and after the clock, with more time than the FF set-up and hold times respectively. QUESTION 10 The simplification strategy used in the Karnaugh Map is based on which of the following Boolean Logic Theorems (Assume notation ( IA) means (NOT A). O a. (A*B) = IA + /B O b. A+ /AB = A + B O C. AB + A/B = A O d. AB + /AC + BC = AB + /AC e (A+B) = /A /B QUESTION 11 Which of the following are types or variations of FSMS mentioned in class? (Mark all that apply.) O a. Timed FSM. O b. None of the above. O C. Recursive FSM. O d. Basic FSM. De. Interacting FSMS. QUESTION 12 Which of the following are true for a Mealy type Finite State Machine. (Mark all that apply.) O a. The values assigned to the Output signals are specified in the Transition branches between states Ob. The VHDL model for Mealy uses a Process() Output Decoder with only the State signal in the sensitivity list. Oc. The values assigned to the Output signals are specified in a State Transition table, but not in the State Transition diagram d. The VHDL model for Mealy uses a Process() for Output Decoder with the Input signals and the State signal on the sensitivity list. De. The values assigned to the Output signals are specified inside the state
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