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variable v_Count : natural range 0 to 5 := 0; begin if rising_ edge(i_clk) then v_Count := v_Count + 1; r_Var_Copy1 <= v_Count; if v Count = 5 then %3D

variable v_Count : natural range 0 to 5 := 0; begin if rising_ edge(i_clk) then v_Count := v_Count + 1; r_Var_Copy1 <= v_Count; if v Count = 5 then %3D

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Explain what the following VHDL code does. [20 marks] EX_VAR : process (i_clk) variable v_Count : natural range 0 to 5 := 0; begin if rising_edge(i_clk) then v_Count := v_Count + 1; 20 21 22 23 24 25 26 r_Var_Copy1 <= v_Count; 27 if v_Count = 5 then r_Done <= '1'; v_Count := 0; else 28 %3D 29 30 31 r_Done <= '0'; end if; 32 33 34 35 r_Var_Copy2 <= v_Count; 36 end if; end process EXx_VAR; 37 38 39 40 o done <= r_Done; 41 42 end rtl;
Transcribed Image Text:Explain what the following VHDL code does. [20 marks] EX_VAR : process (i_clk) variable v_Count : natural range 0 to 5 := 0; begin if rising_edge(i_clk) then v_Count := v_Count + 1; 20 21 22 23 24 25 26 r_Var_Copy1 <= v_Count; 27 if v_Count = 5 then r_Done <= '1'; v_Count := 0; else 28 %3D 29 30 31 r_Done <= '0'; end if; 32 33 34 35 r_Var_Copy2 <= v_Count; 36 end if; end process EXx_VAR; 37 38 39 40 o done <= r_Done; 41 42 end rtl;
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