Using multiple 4M × 8 RAM chips (see below) plus a decoder, construct the block diagram of a 16M × 16 RAM system. Hint: 1 million = 2^20. Please answer the following questions. How many 4M × 8 RAM chips are needed? How many address lines does the memory system require? How many data lines does the memory system require? What kind of address decoder is required? Now design the system below. Be sure you label the memory system inputs, Addr, R/W, and MemSel, and the system’s outputs D0~D15. Also label bus widths, and inputs and outputs of any required decoders. Put a star on the chips containing memory location 0.

Using multiple 4M × 8 RAM chips (see below) plus a decoder, construct the block diagram of a 16M × 16 RAM system. Hint: 1 million = 2^20. Please answer the following questions. How many 4M × 8 RAM chips are needed? How many address lines does the memory system require? How many data lines does the memory system require? What kind of address decoder is required? Now design the system below. Be sure you label the memory system inputs, Addr, R/W, and MemSel, and the system’s outputs D0~D15. Also label bus widths, and inputs and outputs of any required decoders. Put a star on the chips containing memory location 0.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter5: Data Storage Technology

Section: Chapter Questions

Problem 2PE

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Concept explainers

Fundamentals of Input and Output Performance

The I/O subsystem is a component of computer system design that uses buses to assist communication between the Central Processing Unit, Computer Memory/Storage, and Input and Output Devices (that is known as peripheral devices). The I/O subsystem includes disc controllers, tape drives, discs, system buses, and other devices. The I/O database application reads and writes drives using the operating system windows I/O.

Question

Using multiple 4M × 8 RAM chips (see below) plus a decoder, construct the
block diagram of a 16M × 16 RAM system. Hint: 1 million = 2^20.

Please answer the following questions.
How many 4M × 8 RAM chips are needed?
How many address lines does the memory system require?
How many data lines does the memory system require?
What kind of address decoder is required?

Now design the system below. Be sure you label the memory system
inputs, Addr, R/W, and MemSel, and the system’s outputs D0~D15. Also label bus
widths, and inputs and outputs of any required decoders. Put a star on the chips
containing memory location 0.

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