Trace the steps of multiplying a 5-bit two's complement multiplicand (00101), with a 3-bit two's complement multiplier (101)2, using Booth's algorithm. Assume that the shift-add multiplier shown below is used. Initially, the 5 most significant bits of the 8-bit product register contain (00000), and the 3 least significant bits contain the multiplier (101),. When the algorithm completes, the most significant 8-bit of product register must contain the 8-bit product in two's complement representation. Write state of the 9-bit product register (including the least significant bit) after each step shown in the figure above. Initial state: 00000101 o After the 1st add/sub/nop: After the 1st shift: After 2nd add/sub/nop: After the 2nd shift: After 3rd add/sub/nop: After the 3rd shift:

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