The transistor shown in Figure B2 has parameters VTN = 0.4 V, K₂ = 0.4 mA/V², and λ = 0. The transistor is biased at 1pq = 0.8 mA. V₁0- V+ = 2.5 V RD= 1kQ2 Figure B2 1. Draw the small-signal equivalent circuit of the circuit. 2. Determine the maximum small-signal voltage gain. 3. Determine the corner frequency of the circuit. o Vo C₁ = 1 pF
The transistor shown in Figure B2 has parameters VTN = 0.4 V, K₂ = 0.4 mA/V², and λ = 0. The transistor is biased at 1pq = 0.8 mA. V₁0- V+ = 2.5 V RD= 1kQ2 Figure B2 1. Draw the small-signal equivalent circuit of the circuit. 2. Determine the maximum small-signal voltage gain. 3. Determine the corner frequency of the circuit. o Vo C₁ = 1 pF
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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![The transistor shown in Figure B2 has parameters VTN = 0.4 V, K₂ = 0.4 mA/V², and λ = 0. The
transistor is biased at Ipq = 0.8 mA.
1.
V₁0-
Draw the small-signal equivalent circuit of the circuit.
2. Determine the maximum small-signal voltage gain.
Physical Constants &
q=1.602 x 10-19 C
a = 8.854 x 10-¹2 F/m
kB = 1.380 x 10-23 J/K
me = 9.109 x 10-3¹ kg
1 μm = 1 x 10 m
&-Si= 11,7
3. Determine the corner frequency of the circuit.
n, = BT ³/22k7
4. Draw the bode plot of the circuit. The maximum voltage gain (in dB) and corner frequency should
be included.
J₁ = eD₂
V+ = 2.5 V
Drift and Diffusion Currents
J=oE= (1/p)E
dn
dx
Vs
RD=
1kQ
Semiconductor Properties
p-n Junction and Diode Circuits
Vu - KeTmNAND)
Vb =
10 = 1 [exp(27)-1]
V₁N₁
N₂
=
Figure B2
Eg-Si= 1.1 eV
Eg-GaAs = 1.4 eV
Eg-Ge=0.66 eV
nsi = 1.45 x 10¹0 cm3
1 nm 1 x 10⁹ m
d
photocurrent:
Formula Sheet
Box (3.9) x (8.854 x 10-12) F/m
=
n = n.p
V, =
2 fRC
MOS Capacitor and MOSFETS
V=V₂ Ir
source regulation and load regulation:
o enfle + epflh
dp
Jp =-eDp
dx
where f =
-V, In ( NAND)
=
Bsi 5.23 x 10¹5 cm-³ K-3/2
BGaAs = 2.10 x 10¹4 cm³ K-3/2
BGe 1.66 x 10¹5 cm³ K-3/2
μe-si = 1400 cm² V-¹ s-¹
1 pm = 1 x 10-¹2 m
- Vo
C₁ = 1 pF
C =
1
2TP
AVLX100%
AVFS
Ex A
10x
Iph = neDA
C.
√H
1+
V
10 = 1, [exp(-/-)-1]
C₁ =
D_Dr_k₂T
H₂ Hp
=
V₂
μh-Si= 450 cm² V-1 S-1
1 fm = 1 x 10-15 m
VL,no load VL, full load
VL, full lood
Thermal Voltage VT = 0.026 V
Cut-in Voltage V₂ = 0.7 V
Cas
q
-x 100%
Eax
1ax](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F18a59f0a-7c8f-49a1-8487-9703585f340d%2F5d57f033-ccb5-4372-a11e-e9cdf78934ed%2Fi3tdqdf_processed.jpeg&w=3840&q=75)
Transcribed Image Text:The transistor shown in Figure B2 has parameters VTN = 0.4 V, K₂ = 0.4 mA/V², and λ = 0. The
transistor is biased at Ipq = 0.8 mA.
1.
V₁0-
Draw the small-signal equivalent circuit of the circuit.
2. Determine the maximum small-signal voltage gain.
Physical Constants &
q=1.602 x 10-19 C
a = 8.854 x 10-¹2 F/m
kB = 1.380 x 10-23 J/K
me = 9.109 x 10-3¹ kg
1 μm = 1 x 10 m
&-Si= 11,7
3. Determine the corner frequency of the circuit.
n, = BT ³/22k7
4. Draw the bode plot of the circuit. The maximum voltage gain (in dB) and corner frequency should
be included.
J₁ = eD₂
V+ = 2.5 V
Drift and Diffusion Currents
J=oE= (1/p)E
dn
dx
Vs
RD=
1kQ
Semiconductor Properties
p-n Junction and Diode Circuits
Vu - KeTmNAND)
Vb =
10 = 1 [exp(27)-1]
V₁N₁
N₂
=
Figure B2
Eg-Si= 1.1 eV
Eg-GaAs = 1.4 eV
Eg-Ge=0.66 eV
nsi = 1.45 x 10¹0 cm3
1 nm 1 x 10⁹ m
d
photocurrent:
Formula Sheet
Box (3.9) x (8.854 x 10-12) F/m
=
n = n.p
V, =
2 fRC
MOS Capacitor and MOSFETS
V=V₂ Ir
source regulation and load regulation:
o enfle + epflh
dp
Jp =-eDp
dx
where f =
-V, In ( NAND)
=
Bsi 5.23 x 10¹5 cm-³ K-3/2
BGaAs = 2.10 x 10¹4 cm³ K-3/2
BGe 1.66 x 10¹5 cm³ K-3/2
μe-si = 1400 cm² V-¹ s-¹
1 pm = 1 x 10-¹2 m
- Vo
C₁ = 1 pF
C =
1
2TP
AVLX100%
AVFS
Ex A
10x
Iph = neDA
C.
√H
1+
V
10 = 1, [exp(-/-)-1]
C₁ =
D_Dr_k₂T
H₂ Hp
=
V₂
μh-Si= 450 cm² V-1 S-1
1 fm = 1 x 10-15 m
VL,no load VL, full load
VL, full lood
Thermal Voltage VT = 0.026 V
Cut-in Voltage V₂ = 0.7 V
Cas
q
-x 100%
Eax
1ax
![NMOS
Nonsaturation region (ups < ups (sat))
iD = K[2(UGS - VTN)UDS - VDS]
Saturation region (Ups > Ups(sat))
ip = K₁(VGS - VTN)²
Transition point
VDs (sat) = UGS - VTN
Enhancement mode
VTN >0
Depletion mode
VTN<0
K.=+H.C. (H)=+*: (7)
K₂
k
T =
1-1-²-2) -
di D
3) L = [2K (Vasq - VIN)²]*¹ = [2]¹
ON DS
1-poin
i Dar = K₂ (VGs - VIN) ² (1+2VDS)
V₂N =V₂NO+Y(√20, +V'S = √20₁)
= 2K (Vas -VTN) = 2√ √K₂1DQ
ic = IseVBE/VT
¡E = ¹ = ³/VT
iB ==
/Vr
For both transistors
ig=ic + ig
ig = (1+B)iB
α = 1
Bipolar Junction Transistor (BJT)
Summary of the bipolar current-voltage relationships in the active region
NPN
PNP
ic Is exp
, exp (* * *)(1+² =)
V₁B
la
PMOS
Nonsaturation region (USD < Usp (sat))
iD = Kp[2(USG + VTP) USD - USD]
Saturation region (VSD > USD (sat))
ip = K₂(USG + VTP)²
Transition point
VSD (sat) = USG + VTP
Enhancement mode
VTP < 0
Depletion mode
VTP > 0
K‚= ‡μ‚C« (H) = + *; (H)
la
ic=
¡E = ¹ =
iB = 1 =
Iseva/VT
¹/V₂
²¹/V₂
ic = BiB
ic = αig = (+)ie
ß = 12
ro
10](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F18a59f0a-7c8f-49a1-8487-9703585f340d%2F5d57f033-ccb5-4372-a11e-e9cdf78934ed%2Fsu6c8ib_processed.png&w=3840&q=75)
Transcribed Image Text:NMOS
Nonsaturation region (ups < ups (sat))
iD = K[2(UGS - VTN)UDS - VDS]
Saturation region (Ups > Ups(sat))
ip = K₁(VGS - VTN)²
Transition point
VDs (sat) = UGS - VTN
Enhancement mode
VTN >0
Depletion mode
VTN<0
K.=+H.C. (H)=+*: (7)
K₂
k
T =
1-1-²-2) -
di D
3) L = [2K (Vasq - VIN)²]*¹ = [2]¹
ON DS
1-poin
i Dar = K₂ (VGs - VIN) ² (1+2VDS)
V₂N =V₂NO+Y(√20, +V'S = √20₁)
= 2K (Vas -VTN) = 2√ √K₂1DQ
ic = IseVBE/VT
¡E = ¹ = ³/VT
iB ==
/Vr
For both transistors
ig=ic + ig
ig = (1+B)iB
α = 1
Bipolar Junction Transistor (BJT)
Summary of the bipolar current-voltage relationships in the active region
NPN
PNP
ic Is exp
, exp (* * *)(1+² =)
V₁B
la
PMOS
Nonsaturation region (USD < Usp (sat))
iD = Kp[2(USG + VTP) USD - USD]
Saturation region (VSD > USD (sat))
ip = K₂(USG + VTP)²
Transition point
VSD (sat) = USG + VTP
Enhancement mode
VTP < 0
Depletion mode
VTP > 0
K‚= ‡μ‚C« (H) = + *; (H)
la
ic=
¡E = ¹ =
iB = 1 =
Iseva/VT
¹/V₂
²¹/V₂
ic = BiB
ic = αig = (+)ie
ß = 12
ro
10
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