The PIC 12F508/509 block diagram Program memory Data bus for program memory, carrying instruction word Address extracted from instruction word Flash 512 x 12 or 1024 x 12 Program 12 Bus Literal data extracted from instruction word Program Memory OSC1/CLKIN OSC2 to Instruction Reg Instruction Instruction itself! Decode & K Control Timing Generation Internal RC OSC 12 Program Counter Address bus for program memory Stack 1 Stack 2 Direct Addr 5 Device Reset Timer Multiplexer Working register Power-on Reset MCLR Watchdog Timer VDD, VSS Key (See also Key to Figure 1.11) FSR: File Select Register MUX: W reg: GPIO: RC: H Data Bus RAM Addr 9 3 RAM 25 x 8 or 41x8 File Registers Addr MUX ALU 5-7 Addr FSR Reg Status Reg Indirect MUX W Reg Data memory 144 Timero L GPIO Input/ output GPO/SCPDAT GP1/SCPCLK GP2/TOCKI GP3/MCLR/WPP GP4/OSC2 GP5/OSC1/CLKIN Address bus for data memory Data bus for data memory and peripherals General-Purpose Input/Output Resistor capacitor The CPU
The PIC 12F508/509 block diagram Program memory Data bus for program memory, carrying instruction word Address extracted from instruction word Flash 512 x 12 or 1024 x 12 Program 12 Bus Literal data extracted from instruction word Program Memory OSC1/CLKIN OSC2 to Instruction Reg Instruction Instruction itself! Decode & K Control Timing Generation Internal RC OSC 12 Program Counter Address bus for program memory Stack 1 Stack 2 Direct Addr 5 Device Reset Timer Multiplexer Working register Power-on Reset MCLR Watchdog Timer VDD, VSS Key (See also Key to Figure 1.11) FSR: File Select Register MUX: W reg: GPIO: RC: H Data Bus RAM Addr 9 3 RAM 25 x 8 or 41x8 File Registers Addr MUX ALU 5-7 Addr FSR Reg Status Reg Indirect MUX W Reg Data memory 144 Timero L GPIO Input/ output GPO/SCPDAT GP1/SCPCLK GP2/TOCKI GP3/MCLR/WPP GP4/OSC2 GP5/OSC1/CLKIN Address bus for data memory Data bus for data memory and peripherals General-Purpose Input/Output Resistor capacitor The CPU
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
Related questions
Question
Can someone explain the process of the diagram? I am not looking for a particular answer, I just want simple definitions about some of the main components' function... also, sequence or direction of this diagram
Transcribed Image Text:The PIC 12F508/509 block diagram
Program memory
Data bus for
program
memory,
carrying
instruction
word
Address
extracted
from
instruction
word
Program 12
Bus
Literal data
extracted from
instruction word
Instruction
itself!
Flash
512 x 12 or
1024 x 12
OSC1/CLKIN
OSC2
4
Program
Memory
Instruction Reg
Instruction
Decode &
Control
Timing
Generation
Internal RC
OSC
124
Program Counter
Address bus for
program memory
Stack 1
Stack 2
Direct Addr 5
Device Reset
Timer
Multiplexer
W reg: Working register
Power-on
Reset
MCLR
Watchdog
Timer
VDD, VSS
Key (See also Key to Figure 1.11)
FSR:
File Select Register
MUX:
IT
RAM Addr 9
Addr MUX
3
R₂
GPIO:
RC:
Data Bus
8
V
RAM
25 x 8 or
41x8
File
Registers
ALU
5-7 Addr
FSR Reg
Status Reg
MUX
V
W Reg
Data
memory
Indirect
8
Timero
GPIO
Input/
output
GPO/SCPDAT
GP1/SCPCLK
GP2/TOCK!
GP3/MCLR/VPP
GP4/OSC2
GP5/OSC1/CLKIN
Address bus for
data memory
Data bus for data
memory and
peripherals
General-Purpose Input/Output
Resistor capacitor
The CPU
: Notes
DO
80
Expert Solution
Step 1
Functions of peripherals (PIC12F508/509):
• 6 I/O pins:
- 5 I/O pins with individual direction control
- 1 pin for input only
- High voltage sink/source for direct LED power
- Wake-on-change
- Weak strokes
• 8-bit real-time clock/counter (TMR0) with 8-bit
Programmable pre-divider
Step by step
Solved in 3 steps
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